diff options
| author | Nico Huber <nico.h@gmx.de> | 2024-06-01 04:06:12 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2024-11-21 09:24:24 +0000 |
| commit | cae704d236f6c473f29e2f08ad4ce80628d38e5a (patch) | |
| tree | 1d03b37f6b79eb3df25b7d6d5890ca6065a5f0ed /src/northbridge | |
| parent | 22fc6d10d5d7b423fa257d34849ccbe6f8405cc2 (diff) | |
nb/via/cx700: Perform early bootblock init
Disable a timer (GP3) that is always running by default. And enable
SMBus, which is useful this early as a console. The SMBus controller
is mostly compatible to the Intel one.
Change-Id: I77f179433b280d67860fc495605b5764ed081a6c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/via/cx700/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/via/cx700/Makefile.mk | 3 | ||||
| -rw-r--r-- | src/northbridge/via/cx700/bootblock.c | 25 | ||||
| -rw-r--r-- | src/northbridge/via/cx700/early_smbus.c | 8 |
4 files changed, 36 insertions, 1 deletions
diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig index 95f289aacb..f2ba54eee5 100644 --- a/src/northbridge/via/cx700/Kconfig +++ b/src/northbridge/via/cx700/Kconfig @@ -5,6 +5,7 @@ config NORTHBRIDGE_VIA_CX700 select PCI select NO_ECAM_MMCONF_SUPPORT select HAVE_CF9_RESET + select SOUTHBRIDGE_INTEL_COMMON_SMBUS if NORTHBRIDGE_VIA_CX700 diff --git a/src/northbridge/via/cx700/Makefile.mk b/src/northbridge/via/cx700/Makefile.mk index 550ee2dec3..a7af6fd90d 100644 --- a/src/northbridge/via/cx700/Makefile.mk +++ b/src/northbridge/via/cx700/Makefile.mk @@ -1,7 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only ifeq ($(CONFIG_NORTHBRIDGE_VIA_CX700),y) -romstage-y += romstage.c +bootblock-y += early_smbus.c bootblock.c +romstage-y += early_smbus.c romstage.c ramstage-y += chip.c all-y += clock.c reset.c diff --git a/src/northbridge/via/cx700/bootblock.c b/src/northbridge/via/cx700/bootblock.c new file mode 100644 index 0000000000..2de898e8b9 --- /dev/null +++ b/src/northbridge/via/cx700/bootblock.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <static_devices.h> +#include <arch/bootblock.h> + +#define MISC_CONFIG_1 0x94 +#define SMBUS_CLOCK_SELECT (1 << 7) + +#define GP2_GP3_TIMER_CONTROL 0x98 +#define GP3_TIMER_TICK_SELECT (3 << 4) + +#define SMBUS_IO_BASE 0xd0 +#define SMBUS_HOST_CONFIG 0xd2 +#define SMBUS_CLOCK_FROM_128K (1 << 2) +#define SMBUS_ENABLE (1 << 0) + +void bootblock_early_northbridge_init(void) +{ + pci_and_config8(_sdev_lpc, GP2_GP3_TIMER_CONTROL, ~GP3_TIMER_TICK_SELECT); + + pci_and_config8(_sdev_lpc, MISC_CONFIG_1, (u8)~SMBUS_CLOCK_SELECT); /* 14.318MHz */ + pci_write_config16(_sdev_lpc, SMBUS_IO_BASE, CONFIG_FIXED_SMBUS_IO_BASE); + pci_or_config8(_sdev_lpc, SMBUS_HOST_CONFIG, SMBUS_CLOCK_FROM_128K | SMBUS_ENABLE); +} diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c new file mode 100644 index 0000000000..eb8a0f02f9 --- /dev/null +++ b/src/northbridge/via/cx700/early_smbus.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/smbus_host.h> + +uintptr_t smbus_base(void) +{ + return CONFIG_FIXED_SMBUS_IO_BASE; +} |