diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-18 18:03:40 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-06 16:20:08 +0000 |
| commit | afebab1ebe109c7b9ca9820679a4681b996bce0b (patch) | |
| tree | 0cb869b9dbe02822e5e74a241d14b2aa9f583309 /src/northbridge | |
| parent | 898757fc44e73654c8c093a754356820ea42a355 (diff) | |
sb/intel/bd82x6x: assign PCH XHCI controller ops in chipset devicetree
Since the XHCI controller in the PCH is always on the same device
function, the device operations can be statically assigned in the
devicetree and there's no need to bind the XHCI device operations to the
PCI device during runtime via a list of PCI IDs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8685bec734415346a53330c9bd1aa82986995f1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chipset.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index 9cdb6639b4..c304ab4c81 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge device pci 06.0 alias peg60 off end # PEG60 chip southbridge/intel/bd82x6x # Intel Series 6/7 PCH - device pci 14.0 alias xhci off end # USB 3.0 Controller (only on 7 series) + device pci 14.0 alias xhci off ops bd82x6x_usb_xhci_ops end # XHCI Controller only on 7 series device pci 16.0 alias mei1 on end # Management Engine Interface 1 device pci 16.1 alias mei2 off end # Management Engine Interface 2 device pci 16.2 alias me_ide_r off end # Management Engine IDE-R |