mrc_cache: Add mrc_cache fetch functions to support non-x86 platforms

Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):

- mrc_cache_load_current: fetches the mrc_cache data and drops it into
  the given buffer.  This is useful for ARM platforms where the mmap
  operation is very expensive.

- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
  given buffer.  This is useful for platforms where the mmap operation
  is a no-op (like x86 platforms).  As the name mentions, we are not
  freeing the memory that we allocated with the mmap, so it is the
  caller's responsibility to do so.

Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot.  This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).

BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
     reboot from ec console.  Make sure memory training happens.
     reboot from ec console.  Make sure that we don't do training again.

Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 32 insertions, 30 deletions

diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 0b5969249a..9c6c00ff16 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -31,21 +31,24 @@ void save_mrc_data(struct pei_data *pei_data)
 
 static void prepare_mrc_cache(struct pei_data *pei_data)
 {
-	struct region_device rdev;
+	size_t mrc_size;
 
 	/* Preset just in case there is an error */
 	pei_data->mrc_input = NULL;
 	pei_data->mrc_input_len = 0;
 
-	if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev))
+	pei_data->mrc_input =
+		mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+					    MRC_CACHE_VERSION,
+					    &mrc_size);
+	if (!pei_data->mrc_input)
 		/* Error message printed in find_current_mrc_cache */
 		return;
 
-	pei_data->mrc_input = rdev_mmap_full(&rdev);
-	pei_data->mrc_input_len = region_device_sz(&rdev);
+	pei_data->mrc_input_len = mrc_size;
 
-	printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input,
-	       pei_data->mrc_input_len);
+	printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__,
+	       pei_data->mrc_input, mrc_size);
 }
 
 static const char *ecc_decoder[] = {
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index dd1dbd001d..81ba4503a0 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1618,11 +1618,9 @@ static void save_timings(struct raminfo *info)
 
 static const struct ram_training *get_cached_training(void)
 {
-	struct region_device rdev;
-	if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION,
-					&rdev))
-		return 0;
-	return (void *)rdev_mmap_full(&rdev);
+	return mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+					   MRC_CACHE_VERSION,
+					   NULL);
 }
 
 /* FIXME: add timeout.  */
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 06b4d1ec45..6d0e845b56 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -297,7 +297,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 	int me_uma_size, cbmem_was_inited, fast_boot, err;
 	ramctr_timing ctrl;
 	spd_raw_data spds[4];
-	struct region_device rdev;
+	size_t mrc_size;
 	ramctr_timing *ctrl_cached = NULL;
 
 	MCHBAR32(SAPMCTL) |= 1;
@@ -324,10 +324,11 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 	early_thermal_init();
 
 	/* Try to find timings in MRC cache */
-	err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev);
-
-	if (!err && !(region_device_sz(&rdev) < sizeof(ctrl)))
-		ctrl_cached = rdev_mmap_full(&rdev);
+	ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+						  MRC_CACHE_VERSION,
+						  &mrc_size);
+	if (mrc_size < sizeof(ctrl))
+		ctrl_cached = NULL;
 
 	/* Before reusing training data, assert that the CPU has not been replaced */
 	if (ctrl_cached && cpuid != ctrl_cached->cpu) {
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index b6b3989790..5e5cc63c38 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -72,8 +72,8 @@ void save_mrc_data(struct pei_data *pei_data)
 
 static void prepare_mrc_cache(struct pei_data *pei_data)
 {
-	struct region_device rdev;
 	u16 c1, c2, checksum, seed_checksum;
+	size_t mrc_size;
 
 	/* Preset just in case there is an error */
 	pei_data->mrc_input = NULL;
@@ -103,16 +103,18 @@ static void prepare_mrc_cache(struct pei_data *pei_data)
 		return;
 	}
 
-	if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) {
+	pei_data->mrc_input = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+							  MRC_CACHE_VERSION,
+							  &mrc_size);
+	if (pei_data->mrc_input == NULL) {
 		/* Error message printed in find_current_mrc_cache */
 		return;
 	}
 
-	pei_data->mrc_input = rdev_mmap_full(&rdev);
-	pei_data->mrc_input_len = region_device_sz(&rdev);
+	pei_data->mrc_input_len = mrc_size;
 
-	printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input,
-			pei_data->mrc_input_len);
+	printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__,
+	       pei_data->mrc_input, mrc_size);
 }
 
 /**
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 9f361b694e..a62771d676 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -610,8 +610,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 {
 	struct sysinfo s, *ctrl_cached;
 	u8 reg8;
-	int fast_boot, cbmem_was_inited, cache_not_found;
-	struct region_device rdev;
+	int fast_boot, cbmem_was_inited;
+	size_t mrc_size;
 
 	timestamp_add_now(TS_BEFORE_INITRAM);
 	printk(BIOS_DEBUG, "Setting up RAM controller.\n");
@@ -620,10 +620,11 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 
 	memset(&s, 0, sizeof(struct sysinfo));
 
-	cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA,
-						MRC_CACHE_VERSION, &rdev);
+	ctrl_cached = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+						  MRC_CACHE_VERSION,
+						  &mrc_size);
 
-	if (cache_not_found || (region_device_sz(&rdev) < sizeof(s))) {
+	if (!ctrl_cached || mrc_size < sizeof(s)) {
 		if (boot_path == BOOT_PATH_RESUME) {
 			/* Failed S3 resume, reset to come up cleanly */
 			system_reset();
@@ -632,9 +633,6 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 			   and therefore requiring valid cached settings */
 			full_reset();
 		}
-		ctrl_cached = NULL;
-	} else {
-		ctrl_cached = rdev_mmap_full(&rdev);
 	}
 
 	/* verify MRC cache for fast boot */