diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-02-23 16:32:20 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-25 17:44:11 +0000 |
| commit | 972d9f2cce2792b847c4c1879f5b52c19585c37c (patch) | |
| tree | 87166acd957448e6b262a331106e7a276806043c /src/northbridge | |
| parent | 887d4ed912ef80afbf7827150f52e207edc9c033 (diff) | |
arch/x86: consolidate HPET base address definitions
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell_mrc/raminit.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index fedb6832e9..e1a933766a 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/hpet.h> #include <console/console.h> #include <console/usb.h> #include <string.h> @@ -351,7 +352,7 @@ void perform_raminit(const int s3resume) .epbar = CONFIG_FIXED_EPBAR_MMIO_BASE, .pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, - .hpet_address = CONFIG_HPET_ADDRESS, + .hpet_address = HPET_BASE_ADDRESS, .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index cc820cd949..c52203a14e 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/hpet.h> #include <console/console.h> #include <console/usb.h> #include <cf9_reset.h> @@ -235,7 +236,7 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE; pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE; pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS; - pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->hpet_address = HPET_BASE_ADDRESS; pei_data->thermalbase = 0xfed08000; pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE); pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; |