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authorRichard Smith <smithbone@gmail.com>2006-07-29 17:40:36 +0000
committerRichard Smith <smithbone@gmail.com>2006-07-29 17:40:36 +0000
commit924f92faa2f66d09f3ad79a946e3867c105372a7 (patch)
treecf3d183d57d81435ce3382cc0028c48393a99c1b /src/northbridge
parent5e9dc231209c1a293b5a92a9ea78eb07ce0a3086 (diff)
- Add support _framework_ for the Asus p2b.
- New superIO winbond/w83977tf - Add single memory controller SBbus debug routine into a file private to the i440bx This adds support the start of support for an Asus p2b mainboard. Current limitations are the same as for the Bitworks IMS board. Reads from the SMbus don't work. Moving dump_spd_registers() into its own private copy solves the problem of having to go hack on the version that included in src/sdram to only do one memory controller. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i440bx/debug.c91
1 files changed, 91 insertions, 0 deletions
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
new file mode 100644
index 0000000000..77ebcc7b0c
--- /dev/null
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -0,0 +1,91 @@
+
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+ int i;
+ print_debug("\r\n");
+ for(i = 0; i < 4; i++) {
+ unsigned device;
+ device = ctrl->channel0[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(i);
+ print_debug(".0: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = spd_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+#if 0 /* Enable this if you have 2 memory channels */
+ device = ctrl->channel1[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(i);
+ print_debug(".1: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = spd_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+#endif
+ }
+}
+
+#if 0
+void dump_spd_registers(void)
+{
+ unsigned device;
+ device = SMBUS_MEM_DEVICE_START;
+ printk_debug("\n");
+ while(device <= SMBUS_MEM_DEVICE_END) {
+ int status = 0;
+ int i;
+ printk_debug("dimm %02x", device);
+ for(i = 0; (i < 256) && (status == 0); i++) {
+ unsigned char byte;
+ if ((i % 20) == 0) {
+ printk_debug("\n%3d: ", i);
+ }
+ status = smbus_read_byte(device, i, &byte);
+ if (status != 0) {
+ printk_debug("bad device\n");
+ continue;
+ }
+ printk_debug("%02x ", byte);
+ }
+ device += SMBUS_MEM_DEVICE_INC;
+ printk_debug("\n");
+ }
+}
+#endif