summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2021-04-02 19:27:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-04-11 21:05:00 +0000
commit69e3fde5e4b974342dc8be93dd5ec18096e73ebb (patch)
tree1cbd483f50efa98e32bddf8d7f968eaa59b93f66 /src/northbridge
parent527b68219f57f61d1b3f5b50779d22b170ac0f96 (diff)
spd.h: Move `DIMMx` macros to i440bx/raminit.h
These macros aren't needed anywhere else, so reduce their visibility. Change-Id: Ie8d14849b4fb86d34a841d4a13ee3bbb46f9f71c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52061 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i440bx/raminit.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index 1bd5ab6e0f..d2d1729e61 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -6,6 +6,12 @@
/* The 440BX supports up to four (single- or double-sided) DIMMs. */
#define DIMM_SOCKETS 4
+/* DIMM SPD addresses */
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
+
void enable_spd(void);
void disable_spd(void);
void sdram_initialize(int s3resume);