diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-09-28 09:06:43 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-11 21:05:07 +0000 |
| commit | 603963e1ba4147ef31a72b94304708ab416e3b6a (patch) | |
| tree | a6ea32124fe96635dd637333859e7daa6a6e5b73 /src/northbridge | |
| parent | de5d04011cb2f3de4e93381d58a4d01d5682a3f9 (diff) | |
src: Replace MSR addresses with macros
Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/report_platform.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 5b738440f5..04ef3d5ec9 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -50,9 +50,9 @@ static void report_cpu_info(void) microcode_ver.lo = 0; microcode_ver.hi = 0; - wrmsr(0x8B, microcode_ver); + wrmsr(IA32_BIOS_SIGN_ID, microcode_ver); cpuidr = cpuid(1); - microcode_ver = rdmsr(0x8b); + microcode_ver = rdmsr(IA32_BIOS_SIGN_ID); printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpuidr.eax, microcode_ver.hi, cpu_name); aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0; txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0; |