nb/intel/pineview: Native VGA init (CRT)

VGA grub console works but display wobbles left/right

drm/i915 driver reports one error:
- [drm:i915_irq_handler] *ERROR* pipe A underrun
- Monitor does not display 1920x1080 after modeset
- Other resolutions look out of sync

Cause: suspect single bug in raminit (chipset init)

Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12921
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

8 files changed, 522 insertions, 139 deletions

diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 767bb81043..2d10c13e52 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -26,6 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select HAVE_DEBUG_RAM_SETUP
 	select LAPIC_MONOTONIC_TIMER
 	select LATE_CBMEM_INIT
+	select VGA
+	select MAINBOARD_HAS_NATIVE_VGA_INIT
+
+config MAINBOARD_DO_NATIVE_VGA_INIT
+	def_bool y
+	select INTEL_EDID
 
 config BOOTBLOCK_NORTHBRIDGE_INIT
 	string
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index f63018a94c..a4c08c8af1 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -18,6 +18,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_PINEVIEW),y)
 
 ramstage-y += ram_calc.c
 ramstage-y += northbridge.c
+ramstage-y += gma.c
 ramstage-y += acpi.c
 
 romstage-y += ram_calc.c
diff --git a/src/northbridge/intel/pineview/chip.h b/src/northbridge/intel/pineview/chip.h
index a620857157..aabb05eba8 100644
--- a/src/northbridge/intel/pineview/chip.h
+++ b/src/northbridge/intel/pineview/chip.h
@@ -1,8 +1,9 @@
 #include <drivers/intel/gma/i915.h>
 
 struct northbridge_intel_pineview_config {
-	u32 gpu_hotplug;
-	u32 gpu_backlight;
+	/* GMA */
+	bool use_crt;
+	bool use_lvds;
 	int gpu_lvds_use_spread_spectrum_clock;
 	struct i915_gpu_controller_info gfx;
 };
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index dcbdbb13ba..4e968c2038 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -19,82 +19,108 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
+#include <device/pci.h>
 #include <cbmem.h>
 #include <halt.h>
 #include <string.h>
 #include <northbridge/intel/pineview/pineview.h>
+#include <northbridge/intel/pineview/chip.h>
 
 #define LPC PCI_DEV(0, 0x1f, 0)
 #define D0F0 PCI_DEV(0, 0, 0)
 
-static void pineview_setup_bars(void)
+#define PCI_GCFC	0xf0
+#define MCH_GCFGC	0xc8c
+#define  CRCLK_PINEVIEW	0x02
+#define  CDCLK_PINEVIEW	0x10
+#define MCH_HPLLVCO	0xc38
+
+static void early_graphics_setup(void)
 {
 	u8 reg8;
 	u16 reg16;
 	u32 reg32;
 
-	/* Setting up Southbridge. In the northbridge code. */
-	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
-	pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-	pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
-	pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */
-	pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
-	pci_write_config8(LPC, 0x4c /* GC */ , 0x10);	/* Enable GPIOs */
-	pci_write_config32(LPC, 0x88, 0x007c0291);
-
-	pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
-	printk(BIOS_DEBUG, " done.\n");
-
-	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
-	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
-	printk(BIOS_DEBUG, " done.\n");
-
-	/* Enable upper 128bytes of CMOS */
-	RCBA32(0x3400) = (1 << 2);
-
-	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
-	pci_write_config8(D0F0, 0x8, 0x69);
-
-	/* Set up all hardcoded northbridge BARs */
-	pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1);
-	pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
-	pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
-	pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1);
+	const struct device *d0f0 = dev_find_slot(0, PCI_DEVFN(0,0));
+	const struct northbridge_intel_pineview_config *config = d0f0->chip_info;
+
+	pci_write_config8(D0F0, DEVEN, BOARD_DEVEN);
+	pci_write_config16(D0F0, GGC, 0x130); /* 1MB GTT 8MB UMA */
+
+	printk(BIOS_SPEW, "Set GFX clocks...");
+	reg16 = MCHBAR16(MCH_GCFGC);
+	MCHBAR16(MCH_GCFGC) = reg16 | (1 << 9);
+	reg16 &= ~0x7f;
+	reg16 |= CDCLK_PINEVIEW | CRCLK_PINEVIEW;
+	reg16 &= ~(1 << 9);
+	MCHBAR16(MCH_GCFGC) = reg16;
+
+	/* Graphics core */
+	reg8 = MCHBAR8(MCH_HPLLVCO);
+	reg8 &= 0x7;
+
+	reg16 = pci_read_config16(PCI_DEV(0,2,0), 0xcc) & ~0x1ff;
+
+	if (reg8 == 0x4) {
+		/* 2666MHz */
+		reg16 |= 0xad;
+	} else if (reg8 == 0) {
+		/* 3200MHz */
+		reg16 |= 0xa0;
+	} else if (reg8 == 1) {
+		/* 4000MHz */
+		reg16 |= 0xad;
+	}
+
+	pci_write_config16(PCI_DEV(0,2,0), 0xcc, reg16);
+
+	pci_write_config8(PCI_DEV(0,2,0), 0x62,
+		pci_read_config8(PCI_DEV(0,2,0), 0x62) & ~0x3);
+	pci_write_config8(PCI_DEV(0,2,0), 0x62,
+		pci_read_config8(PCI_DEV(0,2,0), 0x62) | 2);
+
+	if (config->use_crt) {
+		/* Enable VGA */
+		MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 15);
+	} else {
+		/* Disable VGA */
+		MCHBAR32(0xb08) = MCHBAR32(0xb08) & ~(1 << 15);
+	}
+
+	if (config->use_lvds) {
+		/* Enable LVDS */
+		reg32 = MCHBAR32(0x3004);
+		reg32 &= ~0xf1000000;
+		reg32 |= 0x90000000;
+		MCHBAR32(0x3004) = reg32;
+		MCHBAR32(0x3008) = MCHBAR32(0x3008) | (1 << 9);
+	} else {
+		/* Disable LVDS */
+		MCHBAR32(0xb08) = MCHBAR32(0xb08) | (3 << 25);
+	}
+
+	MCHBAR32(0xff4) = 0x0c6db8b5f;
+	MCHBAR16(0xff8) = 0x24f;
+
+	MCHBAR32(0xb08) = MCHBAR32(0xb08) & 0xffffff00;
+	MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 5);
+
+	/* Legacy backlight control */
+	pci_write_config8(PCI_DEV(0, 2, 0), 0xf4, 0x4c);
+}
 
+static void early_misc_setup(void)
+{
+	u32 reg32;
 
 	reg32 = MCHBAR32(0x30);
 	MCHBAR32(0x30) = 0x21800;
 	DMIBAR32(0x2c) = 0x86000040;
-	pci_write_config8(D0F0, DEVEN, 0x09);
 	pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200);
 	pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000);
-	reg8 = pci_read_config8(D0F0, 0xe5);  // 0x10
-	reg16 = pci_read_config16(PCI_DEV(0, 0x02, 0), 0x0); // 0x8086
-
-	reg16 = pci_read_config16(D0F0, GGC);
-	pci_write_config16(D0F0, GGC, 0x130);
-	reg16 = pci_read_config16(D0F0, GGC);
-	pci_write_config16(D0F0, GGC, 0x130);
-	MCHBAR8(0xb08) = 0x20;
-	reg8 = pci_read_config8(D0F0, 0xe6); // 0x11
-	reg16 = MCHBAR16(0xc8c);
-	MCHBAR16(0xc8c) = reg16 | 0x0200;
-	reg8 = MCHBAR8(0xc8c);
-	MCHBAR8(0xc8c) = reg8;
-	MCHBAR8(0xc8c) = 0x12;
-	pci_write_config8(PCI_DEV(0, 0x02, 0), 0x62, 0x02);
-	pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe8, 0x8000);
-	MCHBAR32(0x3004) = 0x48000000;
-	MCHBAR32(0x3008) = 0xfffffe00;
-	MCHBAR32(0xb08) = 0x06028220;
-	MCHBAR32(0xff4) = 0xc6db8b5f;
-	MCHBAR16(0xff8) = 0x024f;
-
-	// PLL Voltage controlled oscillator
-	//MCHBAR8(0xc38) = 0x04;
-
-	pci_write_config16(PCI_DEV(0, 0x02, 0), 0xcc, 0x014d);
+
+	early_graphics_setup();
+
 	reg32 = MCHBAR32(0x40);
 	MCHBAR32(0x40) = 0x0;
 	reg32 = MCHBAR32(0x40);
@@ -138,6 +164,38 @@ static void pineview_setup_bars(void)
 	RCBA32(0x3144) = 0x32010237;
 	RCBA32(0x3146) = 0x01463201;
 	RCBA32(0x3148) = 0x146;
+}
+
+static void pineview_setup_bars(void)
+{
+	/* Setting up Southbridge. In the northbridge code. */
+	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
+	pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+	pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1);
+	pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */
+	pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1);
+	pci_write_config8(LPC, 0x4c /* GC */ , 0x10);	/* Enable GPIOs */
+	pci_write_config32(LPC, 0x88, 0x007c0291);
+
+	pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+	printk(BIOS_DEBUG, " done.\n");
+
+	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
+	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
+	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
+	printk(BIOS_DEBUG, " done.\n");
+
+	/* Enable upper 128bytes of CMOS */
+	RCBA32(0x3400) = (1 << 2);
+
+	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
+	pci_write_config8(D0F0, 0x8, 0x69);
+
+	/* Set up all hardcoded northbridge BARs */
+	pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1);
+	pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+	pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+	pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1);
 
 	/* Set C0000-FFFFF to access RAM on both reads and writes */
 	pci_write_config8(D0F0, PAM0, 0x30);
@@ -160,6 +218,9 @@ void pineview_early_initialization(void)
 	/* Setup all BARs required for early PCIe and raminit */
 	pineview_setup_bars();
 
+	/* Miscellaneous set up */
+	early_misc_setup();
+
 	/* Change port80 to LPC */
 	RCBA32(GCS) &= (~0x04);
 	RCBA32(0x2010) |= (1 << 10);
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
new file mode 100644
index 0000000000..989f5ef6da
--- /dev/null
+++ b/src/northbridge/intel/pineview/gma.c
@@ -0,0 +1,332 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ * Copyright (C) 2013 Vladimir Serbinenko
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <device/pci_ops.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+#include <kconfig.h>
+
+#include <drivers/intel/gma/i915_reg.h>
+#include "chip.h"
+#include "pineview.h"
+#include <drivers/intel/gma/intel_bios.h>
+#include <drivers/intel/gma/i915.h>
+#include <pc80/vga.h>
+#include <pc80/vga_io.h>
+
+#define GTTSIZE		(512*1024)
+
+#define PGETBL2_CTL	0x20c4
+#define PGETBL2_1MB	(1 << 8)
+
+#define PGETBL_CTL	0x2020
+#define PGETBL_1MB	(3 << 1)
+#define PGETBL_512KB	0
+#define PGETBL_ENABLED	0x1
+
+#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128   | \
+                           ADPA_CRT_HOTPLUG_WARMUP_10MS  | \
+                           ADPA_CRT_HOTPLUG_MONITOR_COLOR| \
+                           ADPA_CRT_HOTPLUG_SAMPLE_4S    | \
+                           ADPA_CRT_HOTPLUG_VOLTAGE_50   | \
+                           ADPA_CRT_HOTPLUG_VOLREF_325MV | \
+                           ADPA_CRT_HOTPLUG_ENABLE)
+
+static struct resource *gtt_res = NULL;
+static struct resource *mmio_res = NULL;
+
+static int gtt_setup(u8 *mmiobase)
+{
+       u32 gttbase;
+       device_t dev = dev_find_slot(0, PCI_DEVFN(0,0));
+
+       gttbase = pci_read_config32(dev, BGSM);
+       printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
+
+       write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
+       udelay(50);
+       write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
+
+       write32(mmiobase + GFX_FLSH_CNTL, 0);
+
+       return 0;
+}
+
+static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
+	struct device *vga, u8 *mmio, u8 *gtt, u32 physbase, u16 piobase)
+{
+	int i;
+	u32 hactive, vactive;
+	u32 temp;
+
+	printk(BIOS_SPEW, "gtt %x mmio %x addrport %x physbase %x\n",
+		(u32)gtt, (u32)mmio, piobase, physbase);
+
+	gtt_setup(mmio);
+
+	pci_write_config16(vga, 0x52, 0x130);
+
+	/* Disable VGA.  */
+	write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
+
+	/* Disable pipes.  */
+	write32(mmio + PIPECONF(0), 0);
+	write32(mmio + PIPECONF(1), 0);
+
+	write32(mmio + INSTPM, 0x800);
+
+	vga_gr_write(0x18, 0);
+
+	write32(mmio + VGA0, 0x200074);
+	write32(mmio + VGA1, 0x200074);
+
+	write32(mmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
+	write32(mmio + DSPCLK_GATE_D, 0);
+	write32(mmio + FW_BLC, 0x03060106);
+	write32(mmio + FW_BLC2, 0x00000306);
+
+	write32(mmio + ADPA, ADPA_DAC_ENABLE
+			| ADPA_PIPE_A_SELECT
+			| ADPA_HOTPLUG_BITS
+			| ADPA_USE_VGA_HVPOLARITY
+			| ADPA_VSYNC_CNTL_ENABLE
+			| ADPA_HSYNC_CNTL_ENABLE
+			| ADPA_DPMS_ON
+			);
+
+	write32(mmio + 0x7041c, 0x0);
+
+	write32(mmio + DPLL_MD(0), 0x3);
+	write32(mmio + DPLL_MD(1), 0x3);
+	write32(mmio + DSPCNTR(1), 0x1000000);
+	write32(mmio + PIPESRC(1), 0x027f01df);
+
+	vga_misc_write(0x67);
+	const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+		    0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+		    0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
+		    0xff
+	};
+	vga_cr_write(0x11, 0);
+
+	for (i = 0; i <= 0x18; i++)
+		vga_cr_write(i, cr[i]);
+
+	// Disable screen memory to prevent garbage from appearing.
+	vga_sr_write(1, vga_sr_read(1) | 0x20);
+	hactive = 640;
+	vactive = 400;
+
+	mdelay(1);
+	write32(mmio + DPLL(0),
+		DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
+		| DPLL_VGA_MODE_DIS
+		| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
+		| 0x400601
+		);
+	mdelay(1);
+	write32(mmio + DPLL(0),
+		DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
+		| DPLL_VGA_MODE_DIS
+		| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
+		| 0x400601
+		);
+
+	write32(mmio + ADPA, ADPA_DAC_ENABLE
+			| ADPA_PIPE_A_SELECT
+			| ADPA_HOTPLUG_BITS
+			| ADPA_USE_VGA_HVPOLARITY
+			| ADPA_VSYNC_CNTL_ENABLE
+			| ADPA_HSYNC_CNTL_ENABLE
+			| ADPA_DPMS_ON
+			);
+
+	write32(mmio + HTOTAL(1), 0x031f027f);
+	write32(mmio + HBLANK(1), 0x03170287);
+	write32(mmio + HSYNC(1), 0x02ef028f);
+	write32(mmio + VTOTAL(1), 0x020c01df);
+	write32(mmio + VBLANK(1), 0x020401e7);
+	write32(mmio + VSYNC(1), 0x01eb01e9);
+
+	write32(mmio + HTOTAL(0),
+		((hactive - 1) << 16)
+		| (hactive - 1));
+	write32(mmio + HBLANK(0),
+		((hactive - 1) << 16)
+		| (hactive - 1));
+	write32(mmio + HSYNC(0),
+		((hactive - 1) << 16)
+		| (hactive - 1));
+
+	write32(mmio + VTOTAL(0), ((vactive - 1) << 16)
+		| (vactive - 1));
+	write32(mmio + VBLANK(0), ((vactive - 1) << 16)
+		| (vactive - 1));
+	write32(mmio + VSYNC(0),
+		((vactive - 1) << 16)
+		| (vactive - 1));
+
+	write32(mmio + PF_WIN_POS(0), 0);
+
+	write32(mmio + PIPESRC(0), (639 << 16) | 399);
+	write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
+	write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+	write32(mmio + PFIT_CONTROL, 0x0);
+
+	mdelay(1);
+
+	write32(mmio + FDI_RX_CTL(0), 0x00002040);
+	mdelay(1);
+	write32(mmio + FDI_RX_CTL(0), 0x80002050);
+	write32(mmio + FDI_TX_CTL(0), 0x00044000);
+	mdelay(1);
+	write32(mmio + FDI_TX_CTL(0), 0x80044000);
+	write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
+
+	write32(mmio + VGACNTRL, 0x0);
+	write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
+	mdelay(1);
+
+	write32(mmio + ADPA, ADPA_DAC_ENABLE
+			| ADPA_PIPE_A_SELECT
+			| ADPA_HOTPLUG_BITS
+			| ADPA_USE_VGA_HVPOLARITY
+			| ADPA_VSYNC_CNTL_ENABLE
+			| ADPA_HSYNC_CNTL_ENABLE
+			| ADPA_DPMS_ON
+			);
+
+	write32(mmio + DSPFW3, 0x7f3f00c1);
+	write32(mmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
+	write32(mmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
+	write32(mmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
+
+	for (i = 0; i < (8192 - 512) / 4; i++) {
+		outl((i << 2) | 1, piobase);
+		outl(physbase + (i << 12) + 1, piobase + 4);
+	}
+
+	temp = read32(mmio + PGETBL_CTL);
+	printk(BIOS_INFO, "GTT PGETBL_CTL register : 0x%08x\n", temp);
+	temp = read32(mmio + PGETBL2_CTL);
+	printk(BIOS_INFO, "GTT PGETBL2_CTL register: 0x%08x\n", temp);
+
+	/* Clear interrupts. */
+	write32(mmio + DEIIR, 0xffffffff);
+	write32(mmio + SDEIIR, 0xffffffff);
+	write32(mmio + IIR, 0xffffffff);
+	write32(mmio + IMR, 0xffffffff);
+	write32(mmio + EIR, 0xffffffff);
+
+	vga_textmode_init();
+
+	/* Enable screen memory.  */
+	vga_sr_write(1, vga_sr_read(1) & ~0x20);
+}
+
+static void gma_func0_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* IGD needs to be Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) {
+		/* PCI Init, will run VBIOS */
+		pci_dev_init(dev);
+	} else {
+		u32 physbase;
+		struct resource *pio_res;
+		struct northbridge_intel_pineview_config *conf = dev->chip_info;
+
+		/* Find base addresses */
+		mmio_res = find_resource(dev, 0x10);
+		gtt_res = find_resource(dev, 0x1c);
+		pio_res = find_resource(dev, 0x14);
+		physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+
+		if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
+			printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n",
+			       mmio_res->base);
+			intel_gma_init(conf, dev, res2mmio(mmio_res, 0, 0),
+				res2mmio(gtt_res, 0, 0),
+				physbase, pio_res->base);
+		}
+
+		/* Linux relies on VBT for panel info.  */
+		generate_fake_intel_oprom(&conf->gfx, dev,
+			"$VBT PINEVIEW       ");
+	}
+}
+
+static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				   pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				   ((device & 0xffff) << 16) | (vendor &
+								0xffff));
+	}
+}
+
+const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+	if (!dev) {
+		printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n");
+		return NULL;
+	}
+	struct northbridge_intel_pineview_config *chip = dev->chip_info;
+	return &chip->gfx;
+}
+
+static struct pci_operations gma_pci_ops = {
+	.set_subsystem = gma_set_subsystem,
+};
+
+static struct device_operations gma_func0_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.acpi_fill_ssdt_generator = 0,
+	.init = gma_func0_init,
+	.scan_bus = 0,
+	.enable = 0,
+	.ops_pci = &gma_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] =
+{
+	0xa001, 0
+};
+
+static const struct pci_driver gma __pci_driver = {
+	.ops = &gma_func0_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index 0f534dc163..6a3e829f1b 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -29,18 +29,40 @@
 #include <cbmem.h>
 #include <northbridge/intel/pineview/pineview.h>
 
-/* Reserve segments A and B:
+/* Reserve everything between A segment and 1MB:
  *
  * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
  */
 static const int legacy_hole_base_k = 0xa0000 / 1024;
 static const int legacy_hole_size_k = 128;
 
+static void add_fixed_resources(device_t dev, int index)
+{
+	struct resource *resource;
+
+	resource = new_resource(dev, index++);
+	resource->base = (resource_t) 0xfed00000;
+	resource->size = (resource_t) 0x00100000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	mmio_resource(dev, index++, legacy_hole_base_k,
+			(0xc0000 >> 10) - legacy_hole_base_k);
+	reserved_ram_resource(dev, index++, 0xc0000 >> 10,
+			(0x100000 - 0xc0000) >> 10);
+}
+
 static void mch_domain_read_resources(device_t dev)
 {
 	u64 tom, touud;
-	u32 tomk, tolud, uma_sizek = 0, usable_tomk;
+	u32 tomk, tolud, tseg_sizek;
 	u32 pcie_config_base, pcie_config_size;
+	u16 index;
+	const u32 top32memk = 4 * (GiB / KiB);
+
+	index = 3;
 
 	pci_domain_read_resources(dev);
 
@@ -56,15 +78,13 @@ static void mch_domain_read_resources(device_t dev)
 	tom = pci_read_config16(dev, TOM) & 0x1ff;
 	tom <<= 27;
 
-	printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
+	printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx ",
 	       touud, tolud, tom);
 
 	tomk = tolud >> 10;
 
-	/* Graphics memory comes next */
-	const u16 ggc = pci_read_config16(dev, GGC);
-
 	/* Graphics memory */
+	const u16 ggc = pci_read_config16(dev, GGC);
 	const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
 	printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
 	tomk -= gms_sizek;
@@ -74,59 +94,50 @@ static void mch_domain_read_resources(device_t dev)
 	printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
 	tomk -= gsm_sizek;
 
-	uma_sizek = gms_sizek + gsm_sizek;
-
-	usable_tomk = ALIGN_DOWN(tomk, 64 << 10);
-	if (tomk - usable_tomk > (16 << 10))
-		usable_tomk = tomk;
+	const u32 tseg_basek = pci_read_config32(dev, TSEG) >> 10;
+	const u32 igd_basek = pci_read_config32(dev, GBSM) >> 10;
+	const u32 gtt_basek = pci_read_config32(dev, BGSM) >> 10;
 
-	printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
+	/* Subtract TSEG size */
+	tseg_sizek = gtt_basek - tseg_basek;
+	tomk -= tseg_sizek;
 
 	/* Report the memory regions */
-	ram_resource(dev, 3, 0, legacy_hole_base_k);
-	ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
-		     (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k)));
-
-	mmio_resource(dev, 5, legacy_hole_base_k,
-				(0xc0000 >> 10) - legacy_hole_base_k);
+	ram_resource(dev, index++, 0, 640);
+	ram_resource(dev, index++, 768, tomk - 768);
+	reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek);
+	reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek);
+	reserved_ram_resource(dev, index++, igd_basek, gms_sizek);
 
 	/*
-	 * If >= 4GB installed then memory from TOLUD to 4GB
+	 * If > 4GB installed then memory from TOLUD to 4GB
 	 * is remapped above TOM, TOUUD will account for both
 	 */
 	touud >>= 10; /* Convert to KB */
-	if (touud > 4096 * 1024) {
-		ram_resource(dev, 6, 4096 * 1024, touud - (4096 * 1024));
+	if (touud > top32memk) {
+		ram_resource(dev, index++, top32memk, touud - top32memk);
 		printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
-		       (touud >> 10) - 4096);
+		       (touud - top32memk) >> 10);
 	}
 
-	printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
-	       "size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);
-	/* Don't use uma_resource() as our UMA touches the PCI hole. */
-	fixed_mem_resource(dev, 7, tomk, uma_sizek, IORESOURCE_RESERVE);
-
 	if (decode_pciebar(&pcie_config_base, &pcie_config_size)) {
 		printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
-		       "size=0x%x\n", pcie_config_base, pcie_config_size);
-		fixed_mem_resource(dev, 8, pcie_config_base >> 10,
+			"size=0x%x\n", pcie_config_base, pcie_config_size);
+		fixed_mem_resource(dev, index++, pcie_config_base >> 10,
 			pcie_config_size >> 10, IORESOURCE_RESERVE);
 	}
 
+	add_fixed_resources(dev, index);
+
 	set_top_of_ram(tomk << 10);
 }
 
 static void mch_domain_set_resources(device_t dev)
 {
-	struct resource *resource;
-	int i;
+	struct resource *res;
 
-	for (i = 3; i < 9; ++i) {
-		/* Report read resources. */
-		resource = probe_resource(dev, i);
-		if (resource)
-			report_resource_stored(dev, resource, "");
-	}
+	for (res = dev->resource_list; res; res = res->next)
+		report_resource_stored(dev, res, "");
 
 	assign_resources(dev->link_list);
 }
@@ -144,7 +155,6 @@ static void mch_domain_init(device_t dev)
 static struct device_operations pci_domain_ops = {
 	.read_resources   = mch_domain_read_resources,
 	.set_resources    = mch_domain_set_resources,
-	.enable_resources = NULL,
 	.init             = mch_domain_init,
 	.scan_bus         = pci_domain_scan_bus,
 	.ops_pci_bus	  = pci_bus_default_ops,
@@ -160,7 +170,6 @@ static struct device_operations cpu_bus_ops = {
 	.set_resources    = DEVICE_NOOP,
 	.enable_resources = DEVICE_NOOP,
 	.init             = cpu_bus_init,
-	.scan_bus         = 0,
 };
 
 
@@ -190,41 +199,7 @@ static void enable_dev(device_t dev)
 	}
 }
 
-static void pineview_init(void *const chip_info)
-{
-	int dev, fn;
-
-	struct device *const d0f0 = dev_find_slot(0, 0);
-
-	const struct {
-		u8 fn;
-		u8 bitbase;
-	} intfunc[] = {
-		{0, 0},
-		{0, 1}, /* PEG */
-		{1, 3}, /* IGD */
-		{3, 6}, /* ME */
-	};
-
-	/* Hide internal functions based on devicetree info. */
-	for (dev = 3; dev > 0; --dev) {
-		for (fn = intfunc[dev].fn; fn >= 0; --fn) {
-			const struct device *const d =
-				dev_find_slot(0, PCI_DEVFN(dev, fn));
-			if (!d || d->enabled) continue;
-			const u32 deven = pci_read_config32(d0f0, DEVEN);
-			pci_write_config32(d0f0, DEVEN, deven
-				& ~(1 << (intfunc[dev].bitbase + fn)));
-		}
-	}
-
-	const u32 deven = pci_read_config32(d0f0, DEVEN);
-	if (!(deven & (0xf << 6)))
-		pci_write_config32(d0f0, DEVEN, deven & ~(1 << 14));
-}
-
 struct chip_operations northbridge_intel_pineview_ops = {
 	CHIP_NAME("Intel Pineview Northbridge")
 	.enable_dev = enable_dev,
-	.init = pineview_init,
 };
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index d8073402a5..36f0c3c073 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -92,7 +92,6 @@
 #define GMADR		0x18
 #define GTTADR		0x1c
 #define BSM		0x5c
-#define GCFC		0xf0	/* Graphics Clock Frequency & Gating Control */
 
 #define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x))
 
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index a80aeacf8e..a94a2ebb97 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -2057,8 +2057,9 @@ static void sdram_mmap_regs(struct sysinfo *s)
 	reclaimbase = 0;
 	reclaimlimit = 0;
 	ggc = pci_read_config16(PCI_DEV(0,0,0), GGC);
+	printk(BIOS_DEBUG, "GGC = 0x%04x\n", ggc);
 	gfxsize = ggc_to_uma[(ggc & 0xf0) >> 4];
-	gttsize = ggc_to_gtt[(ggc & 0xc00) >> 8];
+	gttsize = ggc_to_gtt[(ggc & 0x300) >> 8];
 	tom = s->channel_capacity[0];
 
 	tsegsize = 0x1; // 1MB
@@ -2085,16 +2086,23 @@ static void sdram_mmap_regs(struct sysinfo *s)
 	tsegbase = gttbase - tsegsize;
 
 	/* Program the regs */
-	pci_write_config16(PCI_DEV(0,0,0), 0xb0, (u16)(tolud << 4));
-	pci_write_config16(PCI_DEV(0,0,0), 0xa0, (u16)(tom >> 6));
+	pci_write_config16(PCI_DEV(0,0,0), TOLUD, (u16)(tolud << 4));
+	pci_write_config16(PCI_DEV(0,0,0), TOM, (u16)(tom >> 6));
 	if (reclaim) {
 		pci_write_config16(PCI_DEV(0,0,0), 0x98, (u16)(reclaimbase >> 6));
 		pci_write_config16(PCI_DEV(0,0,0), 0x9a, (u16)(reclaimlimit >> 6));
 	}
-	pci_write_config16(PCI_DEV(0,0,0), 0xa2, (u16)(touud));
-	pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20);
-	pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20);
-	pci_write_config32(PCI_DEV(0,0,0), 0xac, tsegbase << 20);
+	pci_write_config16(PCI_DEV(0,0,0), TOUUD, (u16)(touud));
+	pci_write_config32(PCI_DEV(0,0,0), GBSM, gfxbase << 20);
+	pci_write_config32(PCI_DEV(0,0,0), BGSM, gttbase << 20);
+	pci_write_config32(PCI_DEV(0,0,0), TSEG, tsegbase << 20);
+
+	printk(BIOS_DEBUG, "GBSM (igd) = verified %08x (written %08x)\n",
+		pci_read_config32(PCI_DEV(0,0,0), GBSM), gfxbase << 20);
+	printk(BIOS_DEBUG, "BGSM (gtt) = verified %08x (written %08x)\n",
+		pci_read_config32(PCI_DEV(0,0,0), BGSM), gttbase << 20);
+	printk(BIOS_DEBUG, "TSEG (smm) = verified %08x (written %08x)\n",
+		pci_read_config32(PCI_DEV(0,0,0), TSEG), tsegbase << 20);
 }
 
 static void sdram_enhancedmode(struct sysinfo *s)