diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-05-06 23:43:46 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-16 17:15:53 +0000 |
| commit | 49509189dc13d467ac2ec2a63b75e30d5f93c9a7 (patch) | |
| tree | 1b845e0051b6188ed7eace6e034a97be23882483 /src/northbridge | |
| parent | 9c8c858e687e03e19773ea84fea021301de0e933 (diff) | |
sb/intel/lynxpoint: Add native PCH init
Implement native PCH initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/native_raminit/raminit_native.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c index dd1f1ec14e..b6efb6b40d 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c @@ -16,8 +16,7 @@ static bool early_init_native(int s3resume) /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/ const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check(); - early_thermal_init(); - early_usb_init(); + early_pch_init_native(s3resume); if (!CONFIG(INTEL_LYNXPOINT_LP)) dmi_early_init(); |