diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-14 09:23:40 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-16 09:54:49 +0000 |
| commit | 3eeefba6a0b1be97b5de70ab9d485f8383472f15 (patch) | |
| tree | 486c110d36932367252551ea9151460500513f59 /src/northbridge | |
| parent | 1515a48cffbb14328e0f68850f60a10332043087 (diff) | |
nb/intel/haswell/memmap.h: Define MMIO window sizes
Add defines for the sizes of northbridge MMIO windows and use them where
applicable. The macro names have been taken from Broadwell.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I845cba8acbd478cd325d2e364138336d985f9c34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/acpi/hostbridge.asl | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/memmap.h | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 12 |
3 files changed, 20 insertions, 10 deletions
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 80d21d0d72..5c22ce1664 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <northbridge/intel/haswell/memmap.h> + Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -173,9 +175,9 @@ Device (PDRC) Name (PDRS, ResourceTemplate () { Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) - Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000) - Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000) - Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE) + Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE) Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index 1aa2d675a6..92beeece49 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -3,6 +3,16 @@ #ifndef NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H #define NORTHBRIDGE_INTEL_HASWELL_MEMMAP_H +#define MCH_BASE_SIZE 0x8000 + +#define DMI_BASE_SIZE 0x1000 + +#define EP_BASE_SIZE 0x1000 + +#define EDRAM_BASE_SIZE 0x4000 + +#define GDXC_BASE_SIZE 0x1000 + #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index fdaac7c311..02799d3f11 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -85,15 +85,13 @@ struct fixed_mmio_descriptor { const char *description; }; -#define SIZE_KB(x) ((x) * 1024) struct fixed_mmio_descriptor mc_fixed_resources[] = { - { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, - { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, - { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, - { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, + { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, + { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, + { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, + { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, }; -#undef SIZE_KB /* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ static void mc_add_fixed_mmio_resources(struct device *dev) |