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authorNico Huber <nico.h@gmx.de>2022-05-14 15:57:31 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-06-24 16:28:33 +0000
commit2a167ffbbfc82e552c8804069986c1091f747105 (patch)
tree4d649d3090c4a1acafb970049c2c901d2396e71e /src/northbridge
parentffd75c29365f1493dc0ef9abdd797653dfb56be6 (diff)
nb/intel/gm45/acpi: Fix max PCI bus number
Commit 0cc56a2848 (nb/intel/gm45/dsdt: Fix number of PCI busses) derives the maximum PCI bus number at runtime. However, IASL complains about the initial 0 in the resource template, which rendered the PB00 definition self-contradictory at build time (maximum was lower than minimum + length - 1). Let's return to the old default values (min: 0, max: 255, length: 256) and adapt max and length at runtime. Also fix some surrounding whites- pace. NB. The issue wasn't detected before merging commit 0cc56a2848 because of broken IASL versions that can't count errors. Change-Id: I359d357f276feda8fe04383080d51dc492c3f2e8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64347 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Ott <coreboot@desire.ch> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/gm45/acpi/hostbridge.asl14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl
index 7c8600341a..0047e19b2a 100644
--- a/src/northbridge/intel/gm45/acpi/hostbridge.asl
+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl
@@ -83,10 +83,9 @@ Device (MCHC)
Name (MCRS, ResourceTemplate()
{
- /* Bus Numbers. Highest bus gets updated later */
+ /* Bus Numbers. Highest bus and length get updated later */
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x0000, 0x0000,
- CONFIG_ECAM_MMCONF_BUS_NUMBER,,, PB00)
+ 0, 0, 255, 0, 256,,, PB00)
/* IO Region 0 */
DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
@@ -208,10 +207,11 @@ External (A4GB, IntObj)
/* Current Resource Settings */
Method (_CRS, 0, Serialized)
{
- /* Set highest PCI bus */
- CreateWordField(MCRS, ^PB00._MAX, BMAX)
- CreateWordField(MCRS, ^PB00._LEN, BLEN)
- BMAX = BLEN - 1
+ /* Set highest PCI bus and length */
+ CreateWordField(MCRS, ^PB00._MAX, BMAX)
+ CreateWordField(MCRS, ^PB00._LEN, BLEN)
+ BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
+ BMAX = BLEN - 1
/* Find PCI resource area in MCRS */
CreateDwordField(MCRS, ^PM01._MIN, PMIN)