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authorDuncan Laurie <dlaurie@chromium.org>2012-06-23 16:53:57 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-24 23:44:40 +0200
commit181bbdd51cb4ec318e8b44c1ca652310bf6abb22 (patch)
tree91489a7a78cea0a7ce3e464f51cbaf4dbb867d20 /src/northbridge
parentf5e9ac48c65bba2876d1dd7f103cd15c5e33c7df (diff)
SMM: Add option for SPI driver to be available in SMM
- add Kconfig option for CONFIG_SPI_FLASH_SMM - compile subsystem and chip drivers for smm if enabled - change mdelay(1) to udelay(500) since mdelay is not defined in SMM and a 1ms delay is worth avoiding - make flash chip structure non-const so the probe function pointers can be relocated for use in TSEG - Make SMM PCI access possible in southbridge SPI code Change-Id: Icfcbbe8e4e56658769d46af0b5bf6c79a6432641 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1313 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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