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authorAngel Pons <th3fanbus@gmail.com>2021-02-10 11:08:28 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-02-16 09:43:07 +0000
commitf5502310e2ad02f4a7c3b98faa3a9a2dadf0525e (patch)
tree956ed47b6ae396a297ea66eaac36d0a0bbd27cbd /src/northbridge
parentfce36e448dcb6346e270bcfa4ec97df09188808e (diff)
nb/intel/sandybridge: Fix description of auto-precharge bit
This bit is primarily used to issue RDA commands. There doesn't seem to be any limitation regarding the number of address bits. Change-Id: I2804f67319c9bc736f9086af408853056aabedd6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c2
-rw-r--r--src/northbridge/intel/sandybridge/registers/mchbar.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 2c16818700..b45c44267c 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1711,7 +1711,7 @@ static void train_write_flyby(ramctr_timing *ctrl)
.rank = slotrank,
},
},
- /* DRAM command RD */
+ /* DRAM command RDA */
[2] = {
.sp_cmd_ctrl = {
.command = IOSAV_RD,
diff --git a/src/northbridge/intel/sandybridge/registers/mchbar.h b/src/northbridge/intel/sandybridge/registers/mchbar.h
index d3df3c0d96..bdf85dc3b3 100644
--- a/src/northbridge/intel/sandybridge/registers/mchbar.h
+++ b/src/northbridge/intel/sandybridge/registers/mchbar.h
@@ -112,7 +112,7 @@
* end architecture RTL;
*
* [16] Chip Select mode control.
- * [17] Auto Precharge. Only valid when using 10 row bits!
+ * [17] Auto Precharge. Used to send RDA commands.
*
* IOSAV_n_SUBSEQ_CTRL_ch(channel, index)
* The parameters of the subseq: number of repetitions of the command,