diff options
| author | Idwer Vollering <vidwer@gmail.com> | 2013-12-22 21:38:18 +0000 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2013-12-23 02:12:51 +0100 |
| commit | d26da9c8f0794f473f476a69821abffb52996237 (patch) | |
| tree | 210ccdfcf6b24b7bc6971aaec964878338c5d2dc /src/northbridge | |
| parent | c6c8cb7f799f81a55b94c1e64ee13773dfc7f631 (diff) | |
Coding style: punctuation cleanup [1/2].
Clean up superfluous line terminators.
Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4562
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i5000/raminit.c | 4 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/detection.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/vx800/freq_setting.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/vx900/raminit_ddr3.c | 4 |
5 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index d6860b2116..8c453321bb 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -48,7 +48,7 @@ static u16 mctGet_NVbits(u8 index) //val = 200; /* 200MHz(DDR400) */ //val = 266; /* 266MHz(DDR533) */ //val = 333; /* 333MHz(DDR667) */ - val = MEM_MAX_LOAD_FREQ;; /* 400MHz(DDR800) */ + val = MEM_MAX_LOAD_FREQ; /* 400MHz(DDR800) */ break; case NV_ECC_CAP: #if SYSTEM_TYPE == SERVER diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 7055c7a1b4..4be7d5d379 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -1283,8 +1283,8 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup) } printk(BIOS_DEBUG, "MIR0: %04x\n", mir0); - printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);; - printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);; + printk(BIOS_DEBUG, "MIR1: %04x\n", mir1); + printk(BIOS_DEBUG, "MIR2: %04x\n", mir2); pci_write_config16(dev16, I5000_MIR0, mir0); pci_write_config16(dev16, I5000_MIR1, mir1); diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c index eb1ddcc2e6..69e520cd8f 100644 --- a/src/northbridge/via/vx800/detection.c +++ b/src/northbridge/via/vx800/detection.c @@ -180,7 +180,7 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr) DramAttr->DimmNumChB++; DramAttr->LoadNumChB = (u8) (DramAttr->LoadNumChB * LoadNum * - RankNum);; + RankNum); } RankNum |= 1; /* Set rank map. */ DramAttr->RankPresentMap |= (RankNum << (Sockets * 2)); diff --git a/src/northbridge/via/vx800/freq_setting.c b/src/northbridge/via/vx800/freq_setting.c index 65b058a32a..55a6316cba 100644 --- a/src/northbridge/via/vx800/freq_setting.c +++ b/src/northbridge/via/vx800/freq_setting.c @@ -65,7 +65,7 @@ void DRAMFreqSetting(DRAM_SYS_ATTR * DramAttr) Data = (u8) ((Data & 0xf8) | 6); break; default: - Data = (u8) ((Data & 0xf8) | 1);; + Data = (u8) ((Data & 0xf8) | 1); } pci_write_config8(MEMCTRL, 0x90, Data); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 1c052c0173..f148ffe82c 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -426,7 +426,7 @@ static void vx900_dram_phys_bank_range(const dimm_info * dimms, } else { /* Otherwise, everything is held in the first bank */ ranks->phys_rank_size_mb[i << 1] = size; - ranks->phys_rank_size_mb[(i << 1) | 1] = 0;; + ranks->phys_rank_size_mb[(i << 1) | 1] = 0; } } } @@ -1294,7 +1294,7 @@ static void vx900_dram_calibrate_transmit_delays(delay_range * tx_dq, { /* Same timeout reasoning as in receive delays */ size_t n_tries = 0; - int dq_tries = 0, dqs_tries = 0;; + int dq_tries = 0, dqs_tries = 0; const size_t max_tries = 100; for (;;) { if (n_tries++ >= max_tries) { |