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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-02-05 09:21:46 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2008-02-05 09:21:46 +0000
commitcb5c9fb9e3e5eb6591b197d9b24f06059400d370 (patch)
tree6d4dcb006f034d075df634088358ef974168d6dc /src/northbridge
parent10aca3cae2c7199027f04f3dfeb5f8df7c0ed8f3 (diff)
Factor out print_conf() from Geode LX mainboard directories. The
following mainboard files had identical Geode LX specific print_conf() implementations: mainboard/amd/db800/mainboard.c mainboard/amd/norwich/mainboard.c mainboard/digitallogic/msm800sev/mainboard.c mainboard/pcengines/alix1c/mainboard.c Move print_conf() to northbridge/amd/lx/northbridge.c where it belongs. Add a copyright notice to mainboard/digitallogic/msm800sev/mainboard.c. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/lx/northbridge.c152
1 files changed, 151 insertions, 1 deletions
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 1e25c2ce04..ead274b729 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -34,6 +34,8 @@
#include <cpu/amd/vr.h>
#include "chip.h"
#include "northbridge.h"
+#include "../../../southbridge/amd/cs5536/cs5536.h"
+
/* here is programming for the various MSRs.*/
#define IM_QWAIT 0x100000
@@ -76,7 +78,6 @@
extern void graphics_init(void);
extern void cpubug(void);
extern void chipsetinit(void);
-extern void print_conf(void);
extern uint32_t get_systop(void);
void northbridge_init_early(void);
@@ -118,6 +119,155 @@ struct msr_defaults {
0}
};
+/* Print the platform configuration - do before PCI init or it will not
+ * work right.
+ */
+void print_conf(void)
+{
+#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+ int i;
+ unsigned long iol;
+ msr_t msr;
+
+ int cpu_msr_defs[] = { CPU_BC_L2_CONF, CPU_IM_CONFIG, CPU_DM_CONFIG0,
+ CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
+ CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
+ GLCP_DELAY_CONTROLS, GL_END
+ };
+
+ int gliu0_msr_defs[] = { MSR_GLIU0_BASE1, MSR_GLIU0_BASE2,
+ MSR_GLIU0_BASE4, MSR_GLIU0_BASE5, MSR_GLIU0_BASE6,
+ GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1, MSR_GLIU0_SYSMEM,
+ GLIU0_P2D_RO_0, GLIU0_P2D_RO_1, GLIU0_P2D_RO_2,
+ MSR_GLIU0_SHADOW, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
+ GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
+ GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
+ GLIU0_GLD_MSR_COH, GL_END
+ };
+
+ int gliu1_msr_defs[] = { MSR_GLIU1_BASE1, MSR_GLIU1_BASE2,
+ MSR_GLIU1_BASE3, MSR_GLIU1_BASE4, MSR_GLIU1_BASE5,
+ MSR_GLIU1_BASE6, MSR_GLIU1_BASE7, MSR_GLIU1_BASE8,
+ MSR_GLIU1_BASE9, MSR_GLIU1_BASE10, GLIU1_P2D_R_0,
+ GLIU1_P2D_R_1, GLIU1_P2D_R_2, GLIU1_P2D_R_3, MSR_GLIU1_SHADOW,
+ GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
+ GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3,
+ GLIU1_GLD_MSR_COH, GL_END
+ };
+
+ int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
+ CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
+ };
+
+ int cs5536_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1,
+ MDD_LEG_IO, MDD_PIN_OPT, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
+ MDD_IRQM_PRIM, GL_END
+ };
+
+ int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
+ GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
+ GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
+ };
+
+ int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
+ MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
+ MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
+ };
+
+ printk_debug("---------- CPU ------------\n");
+
+ for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(cpu_msr_defs[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+ cpu_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- GLIU 0 ------------\n");
+
+ for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(gliu0_msr_defs[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+ gliu0_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- GLIU 1 ------------\n");
+
+ for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
+ msr = rdmsr(gliu1_msr_defs[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n",
+ gliu1_msr_defs[i], msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- RCONF ------------\n");
+
+ for (i = 0; rconf_msr[i] != GL_END; i++) {
+ msr = rdmsr(rconf_msr[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- VARIA ------------\n");
+ msr = rdmsr(0x51300010);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51300010, msr.hi,
+ msr.lo);
+
+ msr = rdmsr(0x51400015);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", 0x51400015, msr.hi,
+ msr.lo);
+
+ printk_debug("---------- DIVIL IRQ ------------\n");
+ msr = rdmsr(MDD_IRQM_YLOW);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YLOW, msr.hi,
+ msr.lo);
+ msr = rdmsr(MDD_IRQM_YHIGH);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_YHIGH,
+ msr.hi, msr.lo);
+ msr = rdmsr(MDD_IRQM_ZLOW);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZLOW, msr.hi,
+ msr.lo);
+ msr = rdmsr(MDD_IRQM_ZHIGH);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_IRQM_ZHIGH,
+ msr.hi, msr.lo);
+
+ printk_debug("---------- PCI ------------\n");
+
+ for (i = 0; pci_msr[i] != GL_END; i++) {
+ msr = rdmsr(pci_msr[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- LPC/UART DMA ------------\n");
+
+ for (i = 0; dma_msr[i] != GL_END; i++) {
+ msr = rdmsr(dma_msr[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ printk_debug("---------- CS5536 ------------\n");
+
+ for (i = 0; cs5536_msr[i] != GL_END; i++) {
+ msr = rdmsr(cs5536_msr[i]);
+ printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", cs5536_msr[i],
+ msr.hi, msr.lo);
+ }
+
+ iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+ printk_debug("IOR 0x%08X is now 0x%08X\n",
+ GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
+ iol = inl(GPIOL_EVENTS_ENABLE);
+ printk_debug("IOR 0x%08X is now 0x%08X\n",
+ GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
+ iol = inl(GPIOL_INPUT_INVERT_ENABLE);
+ printk_debug("IOR 0x%08X is now 0x%08X\n",
+ GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
+ iol = inl(GPIO_MAPPER_X);
+ printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X,
+ iol);
+#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
+}
+
/* todo: add a resource record. We don't do this here because this may be called when
* very little of the platform is actually working.
*/