summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorMatt DeVillier <matt.devillier@gmail.com>2017-11-09 09:45:51 -0600
committerMatt DeVillier <matt.devillier@gmail.com>2017-11-13 16:52:43 +0000
commitc4f9f4bdae57a62ef14a526e51ce2b7d894a0682 (patch)
treed15a7842b401041c23c76ea7999f801c1db665c8 /src/northbridge
parent8e3b5e849cc4437486a33acb1ad4e4b7ce195989 (diff)
google/chell: add missing SPD hex files
Several SPD hex files for chell were missing from upstream coreboot (as compared to the Chromium tree/branch), which resulted in the incorrect type and amount of RAM being reported on chell boards with > 4GB RAM. Add these missing files and their Makefile entries. TEST: boot google/chell m7/16GB config and observe correct RAM type and amount reported via dmidecode and cbmem console log. Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22402 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions