x86: add new mtrr implementation

The old MTRR code had issues using too many variable
MTRRs depending on the physical address space layout dictated
by the device resources. This new implementation calculates
the default MTRR type by comparing the number of variable MTRRs
used for each type. This avoids the need for IORESOURE_UMA_FB
because in many of those situations setting the default type to WB
frees up the variable MTTRs to set that space to UC.

Additionally, it removes the need for IORESOURCE_IGNORE_MTRR
becuase the new mtrr uses the memrange library which does merging
of resources.

Lastly, the sandybridge gma has its speedup optimization removed
for the graphics memory by writing a pre-determined MTRR index.
That will be fixed in an upcoming patch once write-combining support
is added to the resources.

Slight differences from previous MTRR code:
- The number of reserved OS MTRRs is not a hard limit. It's now advisory
  as PAT can be used by the OS to setup the regions to the caching
  policy desired.
- The memory types are calculated once by the first CPU to run the code.
  After that all other CPUs use that value.
- CONFIG_CACHE_ROM support was dropped. It will be added back in its own
  change.

A pathological case that was previously fixed by changing vendor code
to adjust the IO hole location looked like the following:

MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x00000000ad800000 size 0xad740000 type 6
0x00000000ad800000 - 0x00000000d0000000 size 0x22800000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x000000014f600000 size 0x4f600000 type 6

As noted by the output below it's impossible to accomodate those
ranges even with 10 variable MTRRS. However, because the code
can select WB as the default MTRR type it can be done in 6 MTRRs:

MTRR: default type WB/UC MTRR counts: 6/14.
MTRR: WB selected as default type.
MTRR: 0 base 0x00000000ad800000 mask 0x0000007fff800000 type 0
MTRR: 1 base 0x00000000ae000000 mask 0x0000007ffe000000 type 0
MTRR: 2 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 0
MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0

Change-Id: Idfcc78d9afef9d44c769a676716aae3ff2bd79de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 2 insertions, 14 deletions

diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 4a043ebb35..b9a07a2d72 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -622,25 +622,12 @@ static void gma_pm_init_post_vbios(struct device *dev)
 static void gma_func0_init(struct device *dev)
 {
 	u32 reg32;
-	u32 graphics_base, graphics_size;
 
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
 	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
-	/* Set up an MTRR for the graphics memory BAR to vastly improve
-	 * speed of VGA initialization (and later access). To stay out of
-	 * the way of the MTRR init code, we are using MTRR #8 to cover
-	 * that range.
-	 */
-	graphics_base = dev->resource_list[1].base;
-	graphics_size = dev->resource_list[1].size;
-	printk(BIOS_DEBUG, "Setting up MTRR for graphics 0x%08x (%dK)\n",
-				graphics_base, graphics_size / 1024);
-	set_var_mtrr(8, graphics_base >> 10, graphics_size >> 10,
-						MTRR_TYPE_WRCOMB, 0x24);
-
 	/* Init graphics power management */
 	gma_pm_init_pre_vbios(dev);
 
@@ -655,10 +642,11 @@ static void gma_func0_init(struct device *dev)
 #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
 	/* This should probably run before post VBIOS init. */
 	printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
-	u32 iobase, mmiobase, physbase;
+	u32 iobase, mmiobase, physbase, graphics_base;
 	iobase = dev->resource_list[2].base;
 	mmiobase = dev->resource_list[0].base;
 	physbase = pci_read_config32(dev, 0x5c) & ~0xf;
+	graphics_base = dev->resource_list[1].base;
 
 	int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
 	i915lightup(physbase, iobase, mmiobase, graphics_base);