nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhere

Bootblock enabling needs some special handling. Also, the definition of
the `get_pcie_bar` function is incorrect for Ironlake, so remove it.

With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work.
However, it has not been tested. Using 256 busses should still work.

Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 31 insertions, 50 deletions

diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index d371dac729..701c1f92a1 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -18,9 +18,6 @@ config VBOOT
 	# CPU is reset without platform/TPM during romstage
 	select TPM_STARTUP_IGNORE_POSTINIT
 
-config MMCONF_BUS_NUMBER
-	default 256
-
 config CBFS_SIZE
 	hex
 	default 0x100000
@@ -47,6 +44,9 @@ config DCACHE_BSP_STACK_SIZE
 config MMCONF_BASE_ADDRESS
 	default 0xe0000000
 
+config MMCONF_BUS_NUMBER
+	default 256
+
 config INTEL_GMA_BCLV_OFFSET
 	default 0x48254
 
diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c
index 688dd5fd81..97676e7cbb 100644
--- a/src/northbridge/intel/ironlake/acpi.c
+++ b/src/northbridge/intel/ironlake/acpi.c
@@ -1,52 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#define __SIMPLE_DEVICE__
-
-#include <types.h>
-#include <commonlib/helpers.h>
-#include <device/device.h>
-#include <device/pci_ops.h>
+#include <acpi/acpi.h>
 #include "ironlake.h"
 
-static int decode_pcie_bar(u32 *const base, u32 *const len)
-{
-	*base = 0;
-	*len = 0;
-
-	const u32 pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
-
-	if (!(pciexbar_reg & (1 << 0)))
-		return 0;
-
-	switch ((pciexbar_reg >> 1) & 3) {
-	case 0: /* 256MB */
-		*base = pciexbar_reg & (0x0f << 28);
-		*len = 256 * MiB;
-		return 1;
-	case 1: /* 128M */
-		*base = pciexbar_reg & (0x1f << 27);
-		*len = 128 * MiB;
-		return 1;
-	case 2: /* 64M */
-		*base = pciexbar_reg & (0x3f << 26);
-		*len = 64 * MiB;
-		return 1;
-	}
-
-	return 0;
-}
-
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-	u32 length, pciexbar;
-
-	if (!decode_pcie_bar(&pciexbar, &length))
-		return current;
-
-	const int max_buses = length / MiB;
-
-	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
-					     pciexbar, 0x0, 0x0, max_buses - 1);
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
+			CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
 
 	return current;
 }
diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl
index a6e32da381..73242e4503 100644
--- a/src/northbridge/intel/ironlake/acpi/ironlake.asl
+++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl
@@ -15,7 +15,7 @@ Device (PDRC)
 		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00008000)
 		Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
 		Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
-		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
+		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
 		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
 		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
 		Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 89eb81339e..4b174cb0f6 100644
--- a/src/northbridge/intel/ironlake/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -1,11 +1,32 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/bootblock.h>
+#include <assert.h>
 #include <device/pci_ops.h>
+#include <types.h>
 #include "ironlake.h"
 
+static uint32_t encode_pciexbar_length(void)
+{
+	/* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */
+	switch (CONFIG_MMCONF_BUS_NUMBER) {
+		case 256: return 0 << 1;
+		case 128: return 6 << 1;
+		case  64: return 7 << 1;
+		default:  return dead_code_t(uint32_t);
+	}
+}
+
 void bootblock_early_northbridge_init(void)
 {
-	pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1);
-	pci_io_write_config32(QPI_SAD, SAD_PCIEXBAR + 4, 0);
+	/*
+	 * The QuickPath bus number is the topmost bus number, as per the value
+	 * of the SAD_PCIEXBAR register. The register defaults to 256 busses on
+	 * reset. Thus, hardcode the bus number when first setting up PCIEXBAR.
+	 */
+	const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
+
+	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0);
+	pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32);
 }
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 382e0806d9..ac60bcdcef 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -21,7 +21,7 @@
 
 #include "memmap.h"
 
-#define QUICKPATH_BUS 0xff
+#define QUICKPATH_BUS (CONFIG_MMCONF_BUS_NUMBER - 1)
 
 #include <southbridge/intel/ibexpeak/pch.h>