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authorGreg Watson <jarrah@users.sourceforge.net>2004-06-05 14:54:46 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2004-06-05 14:54:46 +0000
commitab8ff84402e97d544b519ec17a2ee184651b8af6 (patch)
treea5e3d276108fbd280b9cd584412c5c9130b0c175 /src/northbridge
parent8ce104f487a8248be143b4436b7a4abc3969bb6f (diff)
Add extra phase before memory init.
Rename sdram_init to memory_init NOTE: need to test sandpoint and ep boards! git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1603 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/ibm/cpc710/cpc710.c12
-rw-r--r--src/northbridge/motorola/mpc107/mpc107.c2
2 files changed, 10 insertions, 4 deletions
diff --git a/src/northbridge/ibm/cpc710/cpc710.c b/src/northbridge/ibm/cpc710/cpc710.c
index 121ecef690..8821850281 100644
--- a/src/northbridge/ibm/cpc710/cpc710.c
+++ b/src/northbridge/ibm/cpc710/cpc710.c
@@ -10,6 +10,7 @@
CPC710_MCCR_FIXED_BITS
void cpc710_init(void);
+void sdram_init(void);
extern void cpc710_pci_init(void);
void
@@ -25,17 +26,16 @@ getCPC710(uint32_t addr)
}
void
-sdram_init(void)
+memory_init(void)
{
cpc710_init();
+ sdram_init();
cpc710_pci_init();
}
void
cpc710_init(void)
{
- uint32_t mccr;
-
setCPC710(CPC710_CPC0_RSTR, 0xf0000000);
(void)getCPC710(CPC710_CPC0_MPSR);
setCPC710(CPC710_CPC0_SIOC0, 0x00000000);
@@ -55,6 +55,12 @@ cpc710_init(void)
setCPC710(CPC710_SDRAM0_MEAR, 0x00000000);
setCPC710(CPC710_SDRAM0_MWPR, 0x00000000);
setCPC710(CPC710_CPC0_RGBAN1, 0x00000000);
+}
+
+void
+sdram_init()
+{
+ uint32_t mccr;
/*
* Reset memory configuration
diff --git a/src/northbridge/motorola/mpc107/mpc107.c b/src/northbridge/motorola/mpc107/mpc107.c
index 00c38e5a0d..8fdc8a9c14 100644
--- a/src/northbridge/motorola/mpc107/mpc107.c
+++ b/src/northbridge/motorola/mpc107/mpc107.c
@@ -35,7 +35,7 @@
void mpc107_init(void);
void
-sdram_init(void)
+memory_init(void)
{
struct sdram_dimm_info dimms[NUM_DIMMS];
struct sdram_bank_info banks[NUM_BANKS];