nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessors

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

6 files changed, 21 insertions, 26 deletions

diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index 701c1f92a1..0d58704a18 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -50,4 +50,13 @@ config MMCONF_BUS_NUMBER
 config INTEL_GMA_BCLV_OFFSET
 	default 0x48254
 
+config FIXED_MCHBAR_MMIO_BASE
+	default 0xfed10000
+
+config FIXED_DMIBAR_MMIO_BASE
+	default 0xfed18000
+
+config FIXED_EPBAR_MMIO_BASE
+	default 0xfed19000
+
 endif
diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl
index d6a2cf8d2f..62ca81a425 100644
--- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl
+++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl
@@ -48,7 +48,7 @@ Device (MCHC)
 	Name (CTCD, 1)		/* CTDP Down Select */
 	Name (CTCU, 2)		/* CTDP Up Select */
 
-	OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
+	OperationRegion (MCHB, SystemMemory, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x8000)
 	Field (MCHB, DWordAcc, Lock, Preserve)
 	{
 		Offset (0x5930),
diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl
index 31af469345..098dd13ab8 100644
--- a/src/northbridge/intel/ironlake/acpi/ironlake.asl
+++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl
@@ -11,9 +11,9 @@ Device (PDRC)
 
 	Name (PDRS, ResourceTemplate() {
 		Memory32Fixed(ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
-		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00008000)
-		Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
-		Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
+		Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE,  0x00001000)
 		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
 		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
 		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index e0120fe078..767db0d3ba 100644
--- a/src/northbridge/intel/ironlake/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -17,12 +17,12 @@ static void ironlake_setup_bars(void)
 {
 	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	/* Set up all hardcoded northbridge BARs */
-	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
-	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0);
+	pci_write_config32(PCI_DEV(0, 0, 0), EPBAR,  CONFIG_FIXED_EPBAR_MMIO_BASE  | 1);
+	pci_write_config32(PCI_DEV(0, 0, 0), EPBAR  + 4, 0);
+	pci_write_config32(PCI_DEV(0, 0, 0), MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1);
+	pci_write_config32(PCI_DEV(0, 0, 0), MCHBAR + 4, 0);
+	pci_write_config32(PCI_DEV(0, 0, 0), DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
+	pci_write_config32(PCI_DEV(0, 0, 0), DMIBAR + 4, 0);
 
 	/* Set C0000-FFFFF to access RAM on both reads and writes */
 	pci_write_config8(QPI_SAD, QPD0F1_PAM(0), 0x30);
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 3a61253b45..cfa16a6d6c 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -88,9 +88,8 @@
  * MCHBAR
  */
 
-#define MCHBAR8(x)			(*((volatile u8  *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR16(x)			(*((volatile u16 *)(DEFAULT_MCHBAR + (x))))
-#define MCHBAR32(x)			(*((volatile u32 *)(DEFAULT_MCHBAR + (x))))
+#include <northbridge/intel/common/fixed_bars.h>
+
 #define MCHBAR8_AND(x,  and)		(MCHBAR8(x)  = MCHBAR8(x)  & (and))
 #define MCHBAR16_AND(x, and)		(MCHBAR16(x) = MCHBAR16(x) & (and))
 #define MCHBAR32_AND(x, and)		(MCHBAR32(x) = MCHBAR32(x) & (and))
@@ -104,20 +103,12 @@
  * EPBAR - Egress Port Root Complex Register Block
  */
 
-#define EPBAR8(x)	(*((volatile u8  *)(DEFAULT_EPBAR + (x))))
-#define EPBAR16(x)	(*((volatile u16 *)(DEFAULT_EPBAR + (x))))
-#define EPBAR32(x)	(*((volatile u32 *)(DEFAULT_EPBAR + (x))))
-
 #include "registers/epbar.h"
 
 /*
  * DMIBAR
  */
 
-#define DMIBAR8(x)	(*((volatile u8  *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR16(x)	(*((volatile u16 *)(DEFAULT_DMIBAR + (x))))
-#define DMIBAR32(x)	(*((volatile u32 *)(DEFAULT_DMIBAR + (x))))
-
 #include "registers/dmibar.h"
 
 #ifndef __ASSEMBLER__
diff --git a/src/northbridge/intel/ironlake/memmap.h b/src/northbridge/intel/ironlake/memmap.h
index cd7708c2f3..2d741400bb 100644
--- a/src/northbridge/intel/ironlake/memmap.h
+++ b/src/northbridge/intel/ironlake/memmap.h
@@ -3,11 +3,6 @@
 #ifndef __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__
 #define __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__
 
-/* Northbridge BARs */
-#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
-#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
-#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
-
 #define IOMMU_BASE1		0xfed90000
 #define IOMMU_BASE2		0xfed91000
 #define IOMMU_BASE3		0xfed92000