diff options
| author | Iru Cai <mytbk920423@gmail.com> | 2020-05-22 22:57:03 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:16:41 +0000 |
| commit | 12a13e1f30a62513d1ade0cef1d5f815b5ddad65 (patch) | |
| tree | 2f5c6d124a36e42e0608a132a0b7d35429543365 /src/northbridge | |
| parent | 27126f135dad3c0e2f91394e7088b2ff50220146 (diff) | |
nb/intel/haswell: Add Crystal Well PCI IDs
From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs
use some new PCI IDs. Without this patch, the Crystal Well northbridge
cannot be initialized in ramstage, thus the machine cannot boot. Some
PCI IDs of Crystal Well related devices can be found in the PCI ID
database [2].
Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. The board
boots to SeaBIOS with boot screen displayed on HDMI output, and then
boots Arch Linux on a USB disk.
[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/DNHLQTNTRQT43T67DG7L2HVI5CV74ZCM/
[2] https://pci-ids.ucw.cz/read/PC/8086
Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41658
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/minihd.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/pcie.c | 5 |
4 files changed, 15 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 68072ff359..c466c09d86 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -108,6 +108,11 @@ u32 map_oprom_vendev(u32 vendev) case 0x8086042a: /* GT3 Server */ case 0x80860a26: /* GT3 ULT */ + case 0x80860d22: /* GT3e Desktop */ + case 0x80860d16: /* GT1 Mobile 4+3 */ + case 0x80860d26: /* GT2 Mobile 4+3, GT3e Mobile */ + case 0x80860d36: /* GT3 Mobile 4+3 */ + new_vendev = 0x80860406; /* GT1 Mobile */ break; } @@ -515,11 +520,12 @@ static const unsigned short pci_device_ids[] = { 0x0402, /* Desktop GT1 */ 0x0412, /* Desktop GT2 */ 0x0422, /* Desktop GT3 */ + 0x0d22, /* Desktop GT3e */ 0x0406, /* Mobile GT1 */ 0x0416, /* Mobile GT2 */ 0x0426, /* Mobile GT3 */ 0x0d16, /* Mobile 4+3 GT1 */ - 0x0d26, /* Mobile 4+3 GT2 */ + 0x0d26, /* Mobile 4+3 GT2, Mobile GT3e */ 0x0d36, /* Mobile 4+3 GT3 */ 0x0a06, /* ULT GT1 */ 0x0a16, /* ULT GT2 */ diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index de2ce06410..1bfbfe5ca0 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -92,7 +92,7 @@ static struct device_operations minihd_ops = { .ops_pci = &pci_dev_ops_pci, }; -static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 }; +static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0x0d0c, 0 }; static const struct pci_driver haswell_minihd __pci_driver = { .ops = &minihd_ops, diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 99621c293b..0a5af4fa7b 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -520,6 +520,9 @@ static const unsigned short mc_pci_device_ids[] = { 0x0c04, /* Mobile */ 0x0a04, /* ULT */ 0x0c08, /* Server */ + 0x0d00, /* Crystal Well Desktop */ + 0x0d04, /* Crystal Well Mobile */ + 0x0d08, /* Crystal Well Server (by extrapolation) */ 0 }; diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index a47a2f507c..d9e77a787a 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -61,7 +61,10 @@ static struct device_operations device_ops = { #endif }; -static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, 0 }; +static const unsigned short pci_device_ids[] = { + 0x0c01, 0x0c05, 0x0c09, 0x0c0d, + 0x0d01, 0x0d05, 0x0d09, /* Crystal Well */ + 0 }; static const struct pci_driver pch_pcie __pci_driver = { .ops = &device_ops, |