diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-12-01 18:14:39 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-04 12:24:25 +0000 |
| commit | f65c1e40885377a07794fc59f38fce1c9230854f (patch) | |
| tree | 610e56fc65eac6d5cab5c0581b0710415a51804c /src/northbridge | |
| parent | 73a544d4533fa8305f1c0a809137b5e2151ea17e (diff) | |
amdblocks/acpimmio: Unify BIOSRAM usage
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at
the source code, every family could have the same API to save and restore
cbmem top or UMA base and size.
Unify BIOSRAM layout and add implementation for cbmem top and UMA storing.
Also replace the existing implementation of cbmem top and UMA with the
BIOSRAM access.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/pi/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/ramtop.c | 33 |
2 files changed, 0 insertions, 36 deletions
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index ffafc6038f..61917c9d48 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -19,7 +19,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 -romstage-y += ramtop.c -postcar-y += ramtop.c -ramstage-y += ramtop.c endif diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/ramtop.c deleted file mode 100644 index 823a15c079..0000000000 --- a/src/northbridge/amd/pi/ramtop.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <device/pci_ops.h> -#include <cbmem.h> - -#define CBMEM_TOP_SCRATCHPAD 0x78 - -void backup_top_of_low_cacheable(uintptr_t ramtop) -{ - uint16_t top_cache = ramtop >> 16; - pci_write_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD, top_cache); -} - -uintptr_t restore_top_of_low_cacheable(void) -{ - uint16_t top_cache; - top_cache = pci_read_config16(PCI_DEV(0,0,0), CBMEM_TOP_SCRATCHPAD); - return (top_cache << 16); -} |