diff options
| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-19 22:09:33 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-03-03 21:09:14 +0100 |
| commit | c7db28c580785b62b9fc67b7526c87d4f0073883 (patch) | |
| tree | 10c118021d5de50d66e826035eab60c391b429c3 /src/northbridge | |
| parent | e1eef694ea6a055ab5f6dc792847702aced5a2ad (diff) | |
intel/nehalem: Fix soft reset detection.
Change-Id: I4575cddc35dc8309372beafec441d194bc145242
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5267
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 46a15a9271..978ffbfb54 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -4970,7 +4970,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) pcie_write_config8(SOUTHBRIDGE, GEN_PMCON_2, pcie_read_config8(SOUTHBRIDGE, GEN_PMCON_2) & ~0x80); udelay(10000); - write_mchbar16(0x2ca8, 0x0); + write_mchbar16(0x2ca8, 0x8); #if REAL udelay(1000); |