Cosmetically make init_cpus more similar for fam10 and K8.

Remove some fam10 warnings.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 48 insertions, 54 deletions

diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 04d06478e2..ab7be4e9e6 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -153,7 +153,9 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink,
 		device_t devx;
 		u32 busses;
 		u32 segn = max>>8;
+#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
 		u32 busn = max&0xff;
+#endif
 		u32 max_devfn;
 
 #if CONFIG_HT3_SUPPORT==1
@@ -332,7 +334,7 @@ static int reg_useable(u32 reg,device_t goal_dev, u32 goal_nodeid,
 			u32 goal_link)
 {
 	struct resource *res;
-	u32 nodeid, link;
+	u32 nodeid, link = 0;
 	int result;
 	res = 0;
 	for(nodeid = 0; !res && (nodeid < NODE_NUMS); nodeid++) {
@@ -646,9 +648,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = {
 
 static void amdfam10_domain_read_resources(device_t dev)
 {
-	struct resource *resource;
 	unsigned reg;
-	unsigned link;
 
 	/* Find the already assigned resource pairs */
 	get_fx_devs();
@@ -658,19 +658,19 @@ static void amdfam10_domain_read_resources(device_t dev)
 		limit = f1_read_config32(reg + 0x04);
 		/* Is this register allocated? */
 		if ((base & 3) != 0) {
-			unsigned nodeid, link;
+			unsigned nodeid, reg_link;
 			device_t reg_dev;
 			if(reg<0xc0) { // mmio
 				nodeid = (limit & 0xf) + (base&0x30);
 			} else { // io
 				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
 			}
-			link   = (limit >> 4) & 7;
+			reg_link   = (limit >> 4) & 7;
 			reg_dev = __f0_dev[nodeid];
 			if (reg_dev) {
 				/* Reserve the resource  */
 				struct resource *reg_resource;
-				reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, link));
+				reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
 				if (reg_resource) {
 					reg_resource->flags = 1;
 				}
@@ -683,6 +683,8 @@ static void amdfam10_domain_read_resources(device_t dev)
 #if CONFIG_PCI_64BIT_PREF_MEM == 0
 	pci_domain_read_resources(dev);
 #else
+	unsigned link;
+	struct resource *resource;
 	for(link=0; link<dev->links; link++) {
 		/* Initialize the system wide io space constraints */
 		resource = new_resource(dev, 0|(link<<2));
@@ -1215,7 +1217,9 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 {
 	struct bus *cpu_bus;
 	device_t dev_mc;
+#if CONFIG_CBB
 	device_t pci_domain;
+#endif
 	int i,j;
 	int nodes;
 	unsigned nb_cfg_54;
@@ -1309,7 +1313,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 	/* Find which cpus are present */
 	cpu_bus = &dev->link[0];
 	for(i = 0; i < nodes; i++) {
-		device_t dev, cpu;
+		device_t cdb_dev, cpu;
 		struct device_path cpu_path;
 		unsigned busn, devn;
 		struct bus *pbus;
@@ -1326,47 +1330,47 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 #endif
 
 		/* Find the cpu's pci device */
-		dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
-		if (!dev) {
+		cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
+		if (!cdb_dev) {
 			/* If I am probing things in a weird order
 			 * ensure all of the cpu's pci devices are found.
 			 */
-			int j;
-			for(j = 0; j <= 5; j++) { //FBDIMM?
-				dev = pci_probe_dev(NULL, pbus,
-					PCI_DEVFN(devn, j));
+			int fn;
+			for(fn = 0; fn <= 5; fn++) { //FBDIMM?
+				cdb_dev = pci_probe_dev(NULL, pbus,
+					PCI_DEVFN(devn, fn));
 			}
-			dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+			cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
 		}
-		if(dev) {
+		if(cdb_dev) {
 			/* Ok, We need to set the links for that device.
 			 * otherwise the device under it will not be scanned
 			 */
-			int j;
+			int link;
 			int linknum;
 #if CONFIG_HT3_SUPPORT==1
 			linknum = 8;
 #else
 			linknum = 4;
 #endif
-			if(dev->links < linknum) {
-				for(j=dev->links; j<linknum; j++) {
-					 dev->link[j].link = j;
-					 dev->link[j].dev = dev;
+			if(cdb_dev->links < linknum) {
+				for(link=cdb_dev->links; link<linknum; link++) {
+					 cdb_dev->link[link].link = link;
+					 cdb_dev->link[link].dev = cdb_dev;
 				}
-				dev->links = linknum;
-				printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(dev), dev->links);
+				cdb_dev->links = linknum;
+				printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(cdb_dev), cdb_dev->links);
 			}
 		}
 
 		cores_found = 0; // one core
-		dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
-		if (dev && dev->enabled) {
-			j = pci_read_config32(dev, 0xe8);
+		cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
+		if (cdb_dev && cdb_dev->enabled) {
+			j = pci_read_config32(cdb_dev, 0xe8);
 			cores_found = (j >> 12) & 3; // dev is func 3
 			if (siblings > 3)
 				cores_found |= (j >> 13) & 4;
-			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(dev), cores_found);
+			printk(BIOS_DEBUG, "  %s siblings=%d\n", dev_path(cdb_dev), cores_found);
 		}
 
 		u32 jj;
@@ -1387,7 +1391,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 			cpu = find_dev_path(cpu_bus, &cpu_path);
 
 			/* Enable the cpu if I have the processor */
-			if (dev && dev->enabled) {
+			if (cdb_dev && cdb_dev->enabled) {
 				if (!cpu) {
 					cpu = alloc_dev(cpu_bus, &cpu_path);
 				}
@@ -1397,7 +1401,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 			}
 
 			/* Disable the cpu if I don't have the processor */
-			if (cpu && (!dev || !dev->enabled)) {
+			if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
 				cpu->enabled = 0;
 			}
 
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 4b33fd6f86..6c36d00f7b 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -17,23 +17,17 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-static  void print_raminit(const char *strval, u32 val)
-{
-	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
-}
-
 static  void print_tx(const char *strval, u32 val)
 {
 #if CONFIG_DEBUG_RAM_SETUP
-	print_raminit(strval, val);
+	printk(BIOS_DEBUG, "%s%08x\n", strval, val);
 #endif
 }
 
 static  void print_t(const char *strval)
 {
 #if CONFIG_DEBUG_RAM_SETUP
-	print_debug(strval);
+	printk(BIOS_DEBUG, "%s", strval);
 #endif
 }
 #include "amdfam10.h"
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index 9542bcb045..148f987023 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -726,13 +726,16 @@ int mctRead_SPD(u32 smaddr, u32 reg);
 void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
 void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
 void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
-static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel);
+void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel);
 void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA);
 u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass);
-static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request);
-static u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct);
-static void mct_Wait(u32 cycles);
+u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct);
+u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly);
+void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request);
+u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct);
+void mct_Wait(u32 cycles);
 u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel);
 u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid);
 void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr);
+void EarlySampleSupport_D(void);
 #endif
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 9dfccd9c4e..170760ddfe 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -582,8 +582,8 @@ skipLocMiddle:
 }
 
 
-static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
-					struct DCTStatStruc *pDCTstat, u8 ChipSel)
+void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
+			struct DCTStatStruc *pDCTstat, u8 ChipSel)
 {
 	/* Store the DQSDelay value, found during a training sweep, into the DCT
 	 * status structure for this node
diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c
index 8087c1c058..961d1f5771 100644
--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c
@@ -17,15 +17,10 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
-static u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct);
-static u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly);
-
 void EarlySampleSupport_D(void)
 {
 }
 
-
 u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val)
 {
 	u32 tmp;
@@ -251,7 +246,7 @@ void SyncSetting(struct DCTStatStruc *pDCTstat)
 }
 
 
-static u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct)
+u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct)
 {
 	u32 ret = 0;
 	u32 lo, hi;
@@ -362,7 +357,7 @@ static u8 mct_checkFenceHoleAdjust_D(struct MCTStatStruc *pMCTstat,
 }
 
 
-static u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly)
+u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly)
 {
 	u8 skip = 0;
 
@@ -393,8 +388,7 @@ static u8 mctDoAxRdPtrInit_D(struct DCTStatStruc *pDCTstat, u8 *Rdtr)
 	return 0;
 }
 
-
-static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) {
+void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) {
 
 	/* Erratum #202: disable DCache scrubber for Ax parts */
 
@@ -403,4 +397,3 @@ static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request)
 		pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis;
 	}
 }
-
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 7b5e1b4b54..0c2a08f8ce 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -502,7 +502,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
 }
 
 
-static u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct)
+u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct)
 {
 	if (pDCTstat->DIMMValidDCT[dct] == 0 ) {
 		return 8;
@@ -1080,7 +1080,7 @@ static void fenceDynTraining_D(struct MCTStatStruc *pMCTstat,
 }
 
 
-static void mct_Wait(u32 cycles)
+void mct_Wait(u32 cycles)
 {
 	u32 saved;
 	u32 hi, lo, msr;