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| author | Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> | 2014-10-14 07:33:53 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-30 12:01:43 +0200 |
| commit | 16110e7ffaf417f98bef2a359ec522f6fc160ee5 (patch) | |
| tree | 1e16f0f6dcc6010856ed3a5c13b2ec990e4512dd /src/northbridge | |
| parent | 9616f3ceb7e6bb2a55b0de01a5364fca011a1ecb (diff) | |
i945/gma: Fix wrong comment about the documentation.
The GTT location is documented in the "309219" datasheet.
For instance it can be found in the TOLUD register description.
The 309219 datasheet is for the
"Mobile Intel® 945 Express Chipset Family". It was published in 2008.
Change-Id: I75ac095ebc577e031af566963ebffe9ed2587c96
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/9622
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/gma.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index cee064081c..e5974c980d 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -58,12 +58,7 @@ static int gtt_setup(void *mmiobase) /* * The Video BIOS places the GTT right below top of memory. - * - * It is not documented in the Intel 945 datasheet, but the Intel - * developers said that it is normally placed there. - * - * TODO: Add option to make the GTT size runtime configurable - */ + */ tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; PGETBL_save = tom - 256 * KiB; PGETBL_save |= PGETBL_ENABLED; |