- unify use of SB_HT_CHAIN_UNITID_OFFSET_ONLY

- cleanup reset
- some minor warning fixes.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5361 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 24 insertions, 15 deletions

diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index e6459d47c3..8e72c656fe 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -57,4 +57,9 @@ config BOOTBLOCK_NORTHBRIDGE_INIT
         default "northbridge/amd/amdfam10/bootblock.c"
 	depends on NORTHBRIDGE_AMD_AMDFAM10
 
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	bool
+	default n
+	depends on NORTHBRIDGE_AMD_AMDFAM10
+
 source src/northbridge/amd/amdfam10/root_complex/Kconfig
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 26b3120f8d..88035aa6c8 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -47,4 +47,9 @@ config HW_MEM_HOLE_SIZE_AUTO_INC
 	default n
 	depends on NORTHBRIDGE_AMD_AMDK8
 
+config SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	bool
+	default n
+	depends on NORTHBRIDGE_AMD_AMDK8
+
 source src/northbridge/amd/amdk8/root_complex/Kconfig
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index a506c07e44..b775813c53 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -7,9 +7,9 @@
 #define HTIC_BIOSR_Detect  (1<<5)
 #define HTIC_INIT_Detect   (1<<6)
 
-static int cpu_init_detected(unsigned nodeid)
+static inline int cpu_init_detected(unsigned nodeid)
 {
-	unsigned long htic;
+	u32 htic;
 	device_t dev;
 
 	dev = PCI_DEV(0, 0x18 + nodeid, 0);
@@ -18,25 +18,25 @@ static int cpu_init_detected(unsigned nodeid)
 	return !!(htic & HTIC_INIT_Detect);
 }
 
-static int bios_reset_detected(void)
+static inline int bios_reset_detected(void)
 {
-	unsigned long htic;
+	u32 htic;
 	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
 
 	return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
 }
 
-static int cold_reset_detected(void)
+static inline int cold_reset_detected(void)
 {
-	unsigned long htic;
+	u32 htic;
 	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
 
 	return !(htic & HTIC_ColdR_Detect);
 }
 
-static void distinguish_cpu_resets(unsigned nodeid)
+static inline void distinguish_cpu_resets(unsigned nodeid)
 {
-	uint32_t htic;
+	u32 htic;
 	device_t device;
 	device = PCI_DEV(0, 0x18 + nodeid, 0);
 	htic = pci_read_config32(device, HT_INIT_CONTROL);
@@ -46,7 +46,7 @@ static void distinguish_cpu_resets(unsigned nodeid)
 
 static void set_bios_reset(void)
 {
-	unsigned long htic;
+	u32 htic;
 	htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
 	htic &= ~HTIC_BIOSR_Detect;
 	pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
@@ -54,10 +54,10 @@ static void set_bios_reset(void)
 
 static unsigned node_link_to_bus(unsigned node, unsigned link)
 {
-	unsigned reg;
+	u8 reg;
 
 	for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-		unsigned config_map;
+		u32 config_map;
 		config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
 		if ((config_map & 3) != 3) {
 			continue;
@@ -71,17 +71,16 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
 	return 0;
 }
 
-static unsigned get_sblk(void)
+static inline unsigned get_sblk(void)
 {
-	uint32_t reg;
+	u32 reg;
 	/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
 	reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
 	return ((reg>>8) & 3) ;
 }
 
-static unsigned get_sbbusn(unsigned sblk)
+static inline unsigned get_sbbusn(unsigned sblk)
 {
 	return node_link_to_bus(0, sblk);
 }
 
-