diff options
| author | Peter Stuge <peter@stuge.se> | 2012-01-27 22:17:09 +0100 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2012-01-31 14:52:22 +0100 |
| commit | 751508ab019e0612f715ea481c550d73aa240112 (patch) | |
| tree | c96ebbd1e82b3c369f0300c1b19d6ba07d12ae48 /src/northbridge | |
| parent | 247c7276938f2ac92944112e218e0d541dff04e9 (diff) | |
northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option
Originally brought up by Sven Schnelle in March 2011
http://patchwork.coreboot.org/patch/2801/
http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html
On some mainboards it may be neccessary to reset early during resume
from S3 if the SLFRCS register indicates that a memory channel is not
guaranteed to be in self-refresh.
On other mainboards, such as Lenovo X60 and T60, the check always
creates false positives, effectively making it impossible to resume.
The SLFRCS register is documented on page 197 of
Mobile Intel® 945 Express Chipset Family Datasheet
Document Number: 309219-006
which is publically available, and the register indicates if a memory
channel is guaranteed to be in self-refresh mode (if bit = 1), or that
a memory channel *may or may not be* in self-refresh mode (if bit = 0).
The register can thus only be used to positively learn that memory is
in self-refresh. It is not known for sure that memory is *not* in
self-refresh. The register is reset by the PWROK signal, which *should*
go low during S3, and go high again when resuming, so it is unsurprising
that SLFRCS has already been cleared when we read the register.
Sven's measurements of the CKE signal on a ThinkPad shows that memory
remains in self-refresh indefinitely, until coreboot re-initializes the
memory controller, even when SLFRCS bits were = 0.
Boards which require a warm reset when SLFRCS bits are cleared must now
explicitly enable the check in the mainboard Kconfig file.
This commit selects the new option in all existing i945 mainboards.
A follow-up commit will remove the option for ThinkPads.
Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/590
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/Kconfig | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 4 |
2 files changed, 11 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 9ba47daf2c..42cc7ce174 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -53,4 +53,13 @@ config MAXIMUM_SUPPORTED_FREQUENCY the board supports, despite what the chipset should be capable of. +config CHECK_SLFRCS_ON_RESUME + def_bool n + help + On some boards it may be neccessary to hard reset early + during resume from S3 if the SLFRCS register indicates that + a memory channel is not guaranteed to be in self-refresh. + On other boards the check always creates a false positive, + effectively making it impossible to resume. + endif diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a7fbaa4439..d92c00672e 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -294,8 +294,8 @@ static void sdram_detect_errors(struct sys_info *sysinfo) reg8 |= (1<<7); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); - /* clear self refresh if not wake-up from suspend */ - if (sysinfo->boot_path != 2) { + /* clear self refresh status if check is disabled or not a resume */ + if (!CONFIG_CHECK_SLFRCS_ON_RESUME || sysinfo->boot_path != 2) { MCHBAR8(0xf14) |= 3; } else { /* Validate self refresh config */ |