cbmem_top: Change the return value to uintptr_t

Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

12 files changed, 21 insertions, 35 deletions

diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index d03639919a..e2ba5542ea 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -117,12 +117,10 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
 	 * RAM to cover both cbmem as the TSEG region.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
 			       MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index dc187911c8..76ca4eea9d 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -81,7 +81,7 @@ static void mch_domain_read_resources(struct device *dev)
 	reserved_ram_from_to(dev, idx++, 0xc0000, 1*MiB);
 
 	/* Report < 4GB memory */
-	ram_range(dev, idx++, 1*MiB, (uintptr_t)cbmem_top());
+	ram_range(dev, idx++, 1*MiB, cbmem_top());
 
 	/* TSEG */
 	uintptr_t tseg_base;
@@ -91,10 +91,10 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* cbmem_top can be shifted downwards due to alignment.
 	   Mark the region between cbmem_top and tseg_base as unusable */
-	if ((uintptr_t)cbmem_top() < tseg_base) {
+	if (cbmem_top() < tseg_base) {
 		printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n",
-		       tseg_base - (uintptr_t)cbmem_top());
-		mmio_from_to(dev, idx++, (uintptr_t)cbmem_top(), tseg_base);
+		       tseg_base - cbmem_top());
+		mmio_from_to(dev, idx++, cbmem_top(), tseg_base);
 	}
 
 	/* graphic memory above TSEG */
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 6b75caa861..82e1d6552f 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -69,12 +69,10 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
 	 * above top of the ram. This satisfies MTRR alignment requirement
 	 * with different TSEG size configurations.
 	 */
-	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB);
+	const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
 }
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 204e83badf..8bdd5d9c6a 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -53,10 +53,8 @@ uintptr_t cbmem_top_chipset(void)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache CBMEM region as WB. */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
 		MTRR_TYPE_WRBACK);
 }
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index e0352fba8f..189f917aa1 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -81,12 +81,10 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
 	 * RAM to cover both cbmem as the TSEG region.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
 			       northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 79e9ee53b8..82f3843d4f 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -34,7 +34,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* Report the memory regions */
 	ram_range(dev, idx++, 0, 0xa0000);
-	ram_from_to(dev, idx++, 1 * MiB, (uintptr_t)cbmem_top());
+	ram_from_to(dev, idx++, 1 * MiB, cbmem_top());
 
 	/* TSEG */
 	uintptr_t tseg_base;
@@ -44,10 +44,10 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* cbmem_top can be shifted downwards due to alignment.
 	   Mark the region between cbmem_top and tseg_base as unusable */
-	if ((uintptr_t)cbmem_top() < tseg_base) {
+	if (cbmem_top() < tseg_base) {
 		printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n",
-		       tseg_base - (uintptr_t)cbmem_top());
-		mmio_from_to(dev, idx++, (uintptr_t)cbmem_top(), tseg_base);
+		       tseg_base - cbmem_top());
+		mmio_from_to(dev, idx++, cbmem_top(), tseg_base);
 	}
 	if (tseg_base + tseg_size < tolud)
 		mmio_from_to(dev, idx++, tseg_base + tseg_size, tolud);
diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c
index bdb76c12bb..cb97c31479 100644
--- a/src/northbridge/intel/ironlake/memmap.c
+++ b/src/northbridge/intel/ironlake/memmap.c
@@ -35,13 +35,11 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
 	 * above top of the ram. This satisfies MTRR alignment requirement
 	 * with different TSEG size configurations.
 	 */
-	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
+	const uintptr_t  top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB);
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
 }
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index 967a59fad0..de2d8400d2 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -86,13 +86,11 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/*
 	 * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both
 	 * CBMEM and the TSEG region.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(),
 			       MTRR_TYPE_WRBACK);
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index c24493aa2b..573f1a8604 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -69,7 +69,7 @@ static void mch_domain_read_resources(struct device *dev)
 
 	/* Report the memory regions */
 	ram_range(dev, index++, 0, 0xa0000);
-	ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
+	ram_from_to(dev, index++, 1 * MiB, cbmem_top());
 	uintptr_t tseg_base;
 	size_t tseg_size;
 	smm_region(&tseg_base, &tseg_size);
@@ -77,8 +77,8 @@ static void mch_domain_read_resources(struct device *dev)
 	mmio_range(dev, index++, gtt_base,  gsm_size);
 	mmio_range(dev, index++, igd_base,  gms_size);
 	printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n",
-	       tseg_base - (uintptr_t)cbmem_top());
-	reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), tseg_base);
+	       tseg_base - cbmem_top());
+	reserved_ram_from_to(dev, index++, cbmem_top(), tseg_base);
 
 	/*
 	 * If > 4GB installed then memory from TOLUD to 4GB
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index ac95ab5683..174c286589 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -67,7 +67,7 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 
 	/*
 	 * Cache 8MiB below the top of ram. On sandybridge systems the top of
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 0b085cf6da..3e6cf113ae 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -84,12 +84,10 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/* Cache 8 MiB region below the top of RAM and 2 MiB above top of
 	 * RAM to cover both cbmem as the TSEG region.
 	 */
-	top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = cbmem_top();
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
 			MTRR_TYPE_WRBACK);
 	postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 4987cae2f1..69eb951702 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -45,7 +45,7 @@ static void mch_domain_read_resources(struct device *dev)
 	ram_from_to(dev, index++, 0, 0xa0000);
 	mmio_from_to(dev, index++, 0xa0000, 0xc0000);
 	reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
-	ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top());
+	ram_from_to(dev, index++, 1 * MiB, cbmem_top());
 
 	/*
 	 * If >= 4GB installed then memory from TOLUD to 4GB
@@ -57,7 +57,7 @@ static void mch_domain_read_resources(struct device *dev)
 	size_t tseg_size;
 	smm_region(&tseg_base, &tseg_size);
 	mmio_from_to(dev, index++, tseg_base, tolud);
-	reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), tseg_base);
+	reserved_ram_from_to(dev, index++, cbmem_top(), tseg_base);
 
 	/* Reserve high memory where the NB BARs are up to 4GiB */
 	mmio_from_to(dev, index++, DEFAULT_HECIBAR, 4ull * GiB);