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authorAngel Pons <th3fanbus@gmail.com>2021-03-26 18:56:16 +0100
committerNico Huber <nico.h@gmx.de>2021-03-28 18:02:31 +0000
commite7a68ec05aaa9906b283adeccf20034d56084ea4 (patch)
tree0241d932edbc4919e91a1027365ac2cd45bdfd9b /src/northbridge
parent7ee1c47cbaccadbba72a9207ad9089792b0e6964 (diff)
nb/intel/pineview/raminit.c: Correct clkset1 programming
Reference code does a 32-bit write, and the values don't fit in 16 bits. Change-Id: I1195c0637b5c215a45328ebae312cf620cd4c950 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51860 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/pineview/raminit.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 680f3c901b..7b9f410327 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -843,8 +843,7 @@ static void sdram_p_clkset0(const struct pllparam *pll, u8 f, u8 i)
/* Program clkset1's register for Kcoarse, Tap, PI, DBEn and DBSel */
static void sdram_p_clkset1(const struct pllparam *pll, u8 f, u8 i)
{
- /* FIXME: This is actually a dword write! */
- MCHBAR16_AND_OR(C0CKTX, ~0x00030880,
+ MCHBAR32_AND_OR(C0CKTX, ~0x00030880,
(pll->clkdelay[f][i] << 16) |
(pll->dben[f][i] << 11) |
(pll->dbsel[f][i] << 7));