device: Use pcidev_path_on_root()

Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

6 files changed, 7 insertions, 7 deletions

diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c
index 9d249e2df4..c9b3ad2a63 100644
--- a/src/northbridge/amd/amdfam10/amdfam10_util.c
+++ b/src/northbridge/amd/amdfam10/amdfam10_util.c
@@ -26,7 +26,7 @@
 #include <include/device/pci_def.h>
 u32 Get_NB32(u32 dev, u32 reg)
 {
-	return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg);
+	return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg);
 }
 #endif
 
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
index fcba7c1457..79775757b5 100644
--- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c
@@ -59,7 +59,7 @@ static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
 	DEVTREE_CONST config_t *config;
 	printk(BIOS_DEBUG, "Configure Default UPD Data\n");
 
-	dev = dev_find_slot(0, SOC_DEV_FUNC);
+	dev = pcidev_path_on_root(SOC_DEV_FUNC);
 	config = dev->chip_info;
 
 	/* Set SPD addresses */
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 2d7965f286..4996c8621a 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1165,7 +1165,7 @@ static unsigned int get_mmio_size(void)
 	const struct device *dev;
 	const struct northbridge_intel_gm45_config *cfg = NULL;
 
-	dev = dev_find_slot(0, HOST_BRIDGE);
+	dev = pcidev_path_on_root(HOST_BRIDGE);
 	if (dev)
 		cfg = dev->chip_info;
 
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 8ae5a4ac0e..106d9a1f09 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -459,7 +459,7 @@ static void disable_devices(void)
 	deven = pci_read_config32(host_dev, DEVEN);
 
 	for (i = 0; i < ARRAY_SIZE(nb_devs); i++) {
-		struct device *dev = dev_find_slot(0, nb_devs[i].devfn);
+		struct device *dev = pcidev_path_on_root(nb_devs[i].devfn);
 		if (!dev || !dev->enabled) {
 			printk(BIOS_DEBUG, "Disabling %s.\n", nb_devs[i].name);
 			deven &= ~nb_devs[i].mask;
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 54ef278840..5a1b26ea92 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -1366,7 +1366,7 @@ static unsigned int get_mmio_size(void)
 	const struct device *dev;
 	const struct northbridge_intel_nehalem_config *cfg = NULL;
 
-	dev = dev_find_slot(0, HOST_BRIDGE);
+	dev = pcidev_path_on_root(HOST_BRIDGE);
 	if (dev)
 		cfg = dev->chip_info;
 
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 4ce059a322..489758135d 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -383,7 +383,7 @@ unsigned int get_mem_min_tck(void)
 	const struct device *dev;
 	const struct northbridge_intel_sandybridge_config *cfg = NULL;
 
-	dev = dev_find_slot(0, HOST_BRIDGE);
+	dev = pcidev_path_on_root(HOST_BRIDGE);
 	if (dev)
 		cfg = dev->chip_info;
 
@@ -449,7 +449,7 @@ static unsigned int get_mmio_size(void)
 	const struct device *dev;
 	const struct northbridge_intel_sandybridge_config *cfg = NULL;
 
-	dev = dev_find_slot(0, HOST_BRIDGE);
+	dev = pcidev_path_on_root(HOST_BRIDGE);
 	if (dev)
 		cfg = dev->chip_info;