diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-07 07:53:38 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-08 11:36:22 +0000 |
| commit | de462804e1ba253285daa4c1ec0edf6da61fbc15 (patch) | |
| tree | 2677a5a1292f14aa85238000098d0ba0b09e42d7 /src/northbridge | |
| parent | a9473ecbb142d07e95b120dbab6e9e50017f1e55 (diff) | |
nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macros
Change-Id: I6d161e9e44ebd284e229ea38b6e23d571aa7bf1e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index cd1f165645..34d1c1f73a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -39,6 +39,7 @@ #include <southbridge/amd/common/reset.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> +#include <cpu/x86/mtrr.h> #include <arch/acpi.h> #include <string.h> #include <device/dram/ddr3.h> @@ -3577,10 +3578,10 @@ retry_dqs_training_and_levelization: mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); if (!is_fam15h()) { /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(0x26C, 0x04040404, 0x04040404); - _WRMSR(0x26D, 0x04040404, 0x04040404); - _WRMSR(0x26E, 0x04040404, 0x04040404); - _WRMSR(0x26F, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_E0000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_E8000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_F0000, 0x04040404, 0x04040404); + _WRMSR(MTRR_FIX_4K_F8000, 0x04040404, 0x04040404); } if (nv_DQSTrainCTL) { |