diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-27 07:24:17 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-28 21:15:27 +0000 |
| commit | d7205bebd53761e17e22701ca0573ffa5629d38e (patch) | |
| tree | 3620a0040d5ae10a4cbce854c9025fb1d50a7016 /src/northbridge | |
| parent | 197a3c6cea86cb92c10c05c710dd4184c0e7ba72 (diff) | |
nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ use
Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/fsp_rangeley/northbridge.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/gm45.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 6 |
5 files changed, 3 insertions, 15 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 160d75477a..8375fbf38c 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -63,9 +63,7 @@ void rangeley_late_initialization(void); u32 sideband_read(int port, int reg); void sideband_write(int port, int reg, long data); -#ifndef __SIMPLE_DEVICE__ void northbridge_acpi_fill_ssdt_generator(struct device *device); -#endif #endif /* #ifndef __ASSEMBLER__ */ #endif /* #ifndef __ACPI__ */ diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 5d437583f2..430afe4077 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -449,12 +449,10 @@ int get_blc_values(const struct blc_pwm_t **entries); u16 get_blc_pwm_freq_value(const char *edid_ascii_string); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif #endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 55c0b4b24b..9de0cfb2c3 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -208,24 +208,20 @@ #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); } -#ifdef __SMM__ void intel_northbridge_haswell_finalize_smm(void); -#else /* !__SMM__ */ + void haswell_early_initialization(int chipset_type); void haswell_late_initialization(void); void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void); void report_platform_info(void); -#endif /* !__SMM__ */ -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif #endif #endif diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index b488f2c249..b598c9b6e9 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -227,12 +227,10 @@ int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); enum platform_type get_platform_type(void); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include <device/device.h> struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif #endif #endif diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 57723364ab..05479a1602 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -368,7 +368,6 @@ enum ddr2_signals { CTRL3, }; -#ifndef __BOOTBLOCK__ void x4x_early_init(void); void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); @@ -411,10 +410,9 @@ extern const u32 ddr3_c2_tab[2][3][6][2]; extern const u8 ddr3_c2_x264[3][6]; extern const u16 ddr3_c2_x23c[3][6]; +#include <device/device.h> struct acpi_rsdp; -#ifndef __SIMPLE_DEVICE__ unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif /* __SIMPLE_DEVICE__ */ -#endif + #endif /* __NORTHBRIDGE_INTEL_X4X_H__ */ |