diff options
| author | Petr Cvek <petrcvekcz@gmail.com> | 2022-04-21 04:31:39 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-22 21:35:35 +0000 |
| commit | b30f8687b2a097c85b87b65b392833d43566c9d1 (patch) | |
| tree | 4c33e9036ae156dcabaa7324676a641948faaaf4 /src/northbridge | |
| parent | b94d3681e1c0f96f026ce0e2fbc64759f070b580 (diff) | |
nb/intel/i945/memmap.c: Fix TOLUD bit field mask
Register TOLUD is defined as bit field 7:3 (section 5.1.26, page 103,
i945GM datasheet), fix the mask accordingly.
Change-Id: Ia27661084e11ea93d5f0dc20bafb488ae2995b49
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/memmap.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 1dea21c6d6..58e29c8107 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -40,7 +40,7 @@ static uintptr_t northbridge_get_tseg_base(void) /* IGD enabled, get top of Memory from BSM register */ tom = pci_read_config32(IGD_DEV, BSM); else - tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf7) << 24; + tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf8) << 24; /* subtract TSEG size */ tom -= decode_tseg_size(pci_read_config8(HOST_BRIDGE, ESMRAMC)); |