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authorElyes HAOUAS <ehaouas@noos.fr>2021-01-16 14:59:42 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-01-18 07:36:31 +0000
commit98d6f33c0bc15567b340174c610e590210f5af12 (patch)
treeb60dbce6c6e40e7bf992100de0bd2878762d229f /src/northbridge
parent5323bf422f81d2ae8babe7a1c2c0a59068b0992d (diff)
northbridge/intel/sandybridge/bootblock.c: Remove repeated word
Change-Id: I9e723e1d31b093a4781413efe7f290a295b833dc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/sandybridge/bootblock.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index dad61f9ee8..bea85f4f8e 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -10,7 +10,7 @@ void bootblock_early_northbridge_init(void)
/*
* The "io" variant of the config access is explicitly used to setup the
- * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to to true. That way, all
+ * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the