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authorAaron Durbin <adurbin@chromium.org>2015-05-15 23:39:23 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-06-02 14:09:31 +0200
commit899d13d0dff9e7495eb17950f19431e9bd344b2f (patch)
tree8901845fc299126a7125ff19fe1f7bde17e3f305 /src/northbridge
parent68bdd00799c7b2b25f265fa9e31beb709c877eb6 (diff)
cbfs: new API and better program loading
A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. The program loading takes advantage of those very properties by allowing multiple sources for locating a program. Because of this we can reduce the overhead of loading programs because it's all done in the common code paths. Only locating the program is per source. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9134 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/agesa/common/common.c3
-rw-r--r--src/northbridge/amd/agesa/def_callouts.c4
-rw-r--r--src/northbridge/amd/pi/agesawrapper.c11
-rw-r--r--src/northbridge/amd/pi/def_callouts.c4
-rw-r--r--src/northbridge/intel/haswell/mrccache.c3
-rw-r--r--src/northbridge/intel/haswell/raminit.c4
-rw-r--r--src/northbridge/intel/i82830/vga.c3
-rw-r--r--src/northbridge/intel/sandybridge/mrccache.c3
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c3
9 files changed, 14 insertions, 24 deletions
diff --git a/src/northbridge/amd/agesa/common/common.c b/src/northbridge/amd/agesa/common/common.c
index a77aea7d55..cc08ac1637 100644
--- a/src/northbridge/amd/agesa/common/common.c
+++ b/src/northbridge/amd/agesa/common/common.c
@@ -38,7 +38,8 @@ AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
char *spd_file;
- spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", CBFS_TYPE_SPD_BIN, &spd_file_length);
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD_BIN,
+ &spd_file_length);
if (!spd_file)
die("file [spd.bin] not found in CBFS");
diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c
index fd3ceee188..c07c063f00 100644
--- a/src/northbridge/amd/agesa/def_callouts.c
+++ b/src/northbridge/amd/agesa/def_callouts.c
@@ -117,8 +117,8 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt)
{
GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt;
- pVbiosImageInfo->ImagePtr = cbfs_get_file_content(
- CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom",
+ pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak(
+ "pci"CONFIG_VGA_BIOS_ID".rom",
CBFS_TYPE_OPTIONROM, NULL);
/* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */
return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS;
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 247a38f716..1236932626 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -593,20 +593,13 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus)
const void *agesawrapper_locate_module (const CHAR8 name[8])
{
- struct cbfs_media media;
- struct cbfs_file* file;
const void* agesa;
const AMD_IMAGE_HEADER* image;
const AMD_MODULE_HEADER* module;
size_t file_size;
- if (init_default_cbfs_media(&media))
- return NULL;
- file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME);
- if (!file)
- return NULL;
- agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME,
- ntohl(file->type), &file_size);
+ agesa = cbfs_boot_map_with_leak((const char *)CONFIG_CBFS_AGESA_NAME,
+ CBFS_TYPE_RAW, &file_size);
if (!agesa)
return NULL;
image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name);
diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c
index 0ff7f457fe..8a4472ccc4 100644
--- a/src/northbridge/amd/pi/def_callouts.c
+++ b/src/northbridge/amd/pi/def_callouts.c
@@ -107,8 +107,8 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt)
{
GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt;
- pVbiosImageInfo->ImagePtr = cbfs_get_file_content(
- CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom",
+ pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak(
+ "pci"CONFIG_VGA_BIOS_ID".rom",
CBFS_TYPE_OPTIONROM, NULL);
printk(BIOS_DEBUG, "agesa_GfxGetVbiosImage: IMGptr=%p\n", pVbiosImageInfo->ImagePtr);
return (pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING);
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index d72c2c3224..481110f2fe 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -74,8 +74,7 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
*mrc_region_ptr = rdev_mmap_full(&rdev);
}
} else {
- *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "mrc.cache",
+ *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache",
CBFS_TYPE_MRC_CACHE,
&region_size);
}
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 9bb1d8af61..86205abc24 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -162,8 +162,8 @@ void sdram_initialize(struct pei_data *pei_data)
pei_data->tx_byte = do_putchar;
/* Locate and call UEFI System Agent binary. */
- entry = (unsigned long)cbfs_get_file_content(
- CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL);
+ entry = (unsigned long)cbfs_boot_map_with_leak("mrc.bin",
+ CBFS_TYPE_MRC, NULL);
if (entry) {
int rv;
asm volatile (
diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c
index 0fd197b7ff..7a79d13b81 100644
--- a/src/northbridge/intel/i82830/vga.c
+++ b/src/northbridge/intel/i82830/vga.c
@@ -31,8 +31,7 @@ static void vga_init(device_t dev)
{
printk(BIOS_INFO, "Starting Graphics Initialization\n");
size_t mbi_len;
- void *mbi = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mbi.bin",
- CBFS_TYPE_MBI, &mbi_len);
+ void *mbi = cbfs_boot_map_with_leak("mbi.bin", CBFS_TYPE_MBI, &mbi_len);
if (mbi && mbi_len) {
/* The GDT or coreboot table is going to live here. But
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index e17c54b7cd..94a7c396fb 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -74,8 +74,7 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
*mrc_region_ptr = rdev_mmap_full(&rdev);
}
} else {
- *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA,
- "mrc.cache",
+ *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache",
CBFS_TYPE_MRC_CACHE,
&region_size);
}
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 3cf0726d6a..053a4873cd 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -246,8 +246,7 @@ void sdram_initialize(struct pei_data *pei_data)
pei_data->tx_byte = do_putchar;
/* Locate and call UEFI System Agent binary. */
- entry = cbfs_get_file_content(
- CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL);
+ entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL);
if (entry) {
int rv;
rv = entry (pei_data);