diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-15 12:59:57 +0200 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-08-02 14:59:45 +0000 |
| commit | 863efe45459a836bcb1115901e832d0a41e0b433 (patch) | |
| tree | c2ab070dd3e85a261ac7a048ab4cb2424e0d74f7 /src/northbridge | |
| parent | bc04997f75dfed7d58212565a45f8f51d7473e70 (diff) | |
nb/intel/haswell: Move MRC glue code into a subfolder
Put the Haswell MRC glue code inside a `haswell_mrc` subfolder. Future
commits will move the Broadwell MRC/refcode glue code to be in Haswell
northbridge scope, so plan in advance.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55523
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/Makefile.inc | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/haswell_mrc/Makefile.inc | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/haswell_mrc/pei_data.h (renamed from src/northbridge/intel/haswell/pei_data.h) | 0 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/haswell_mrc/raminit.c (renamed from src/northbridge/intel/haswell/raminit.c) | 4 |
4 files changed, 13 insertions, 9 deletions
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index f718f9a1af..2d1532be05 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -13,17 +13,12 @@ ramstage-y += acpi.c ramstage-y += minihd.c romstage-y += memmap.c -romstage-y += raminit.c romstage-y += romstage.c romstage-y += early_init.c romstage-y += report_platform.c -# We don't ship that, but booting without it is bound to fail -cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin -mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) -mrc.bin-position := 0xfffa0000 -mrc.bin-type := mrc - postcar-y += memmap.c +subdirs-y += haswell_mrc + endif diff --git a/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc b/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc new file mode 100644 index 0000000000..bd6314cc01 --- /dev/null +++ b/src/northbridge/intel/haswell/haswell_mrc/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += raminit.c + +# We don't ship that, but booting without it is bound to fail +cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin +mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) +mrc.bin-position := 0xfffa0000 +mrc.bin-type := mrc diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/haswell_mrc/pei_data.h index c455e17d45..c455e17d45 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/haswell_mrc/pei_data.h diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 45377839bc..338b4d0c41 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -14,6 +14,8 @@ #include <device/pci_ops.h> #include <device/dram/ddr3.h> #include <northbridge/intel/haswell/chip.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> #include <smbios.h> #include <spd.h> #include <security/vboot/vboot_common.h> @@ -23,9 +25,7 @@ #include <timestamp.h> #include <types.h> -#include "raminit.h" #include "pei_data.h" -#include "haswell.h" #define MRC_CACHE_VERSION 1 |