diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-26 12:20:46 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-03-28 18:00:49 +0000 |
| commit | 7adfe80469e32e10db0387b395c16d6494a0cd8e (patch) | |
| tree | ddc099d44e52d78472b3111d42e8cbe29f2106a1 /src/northbridge | |
| parent | 498f1285d2b7227c0f0e52ad5ed43c249412d907 (diff) | |
nb/intel/haswell: Replace `DMIBAR64` and `EPBAR64`
While 64-bit writes seem to work properly, there could be unknown
side-effects in some cases, e.g. when running in long mode. Since
reference code uses two 32-bit writes, follow suit.
Change-Id: I48ed3d94c7865b3a3cce52108e99cf1656b57fc2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51855
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 12 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 2001f7b038..a37238fef7 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -82,16 +82,12 @@ * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR64(x) (*((volatile u64 *)((uintptr_t)CONFIG_FIXED_EPBAR_MMIO_BASE + (x)))) - #include "registers/epbar.h" /* * DMIBAR */ -#define DMIBAR64(x) (*((volatile u64 *)((uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE + (x)))) - #include "registers/dmibar.h" #ifndef __ASSEMBLER__ diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ab42e721d1..3494422438 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -469,7 +469,8 @@ static void northbridge_topology_init(void) reg32 &= ~(0xff << 16); reg32 |= 1 | (1 << 16); EPBAR32(EPLE1D) = reg32; - EPBAR64(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; + EPBAR32(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; + EPBAR32(EPLE1A + 4) = 0; for (unsigned int i = 0; i <= 2; i++) { const struct device *const dev = pcidev_on_root(1, i); @@ -477,7 +478,8 @@ static void northbridge_topology_init(void) if (!dev || !dev->enabled) continue; - EPBAR64(eple_a[i]) = (u64)PCI_DEV(0, 1, i); + EPBAR32(eple_a[i]) = (u32)PCI_DEV(0, 1, i); + EPBAR32(eple_a[i] + 4) = 0; reg32 = EPBAR32(eple_d[i]); reg32 &= ~(0xff << 16); @@ -503,9 +505,11 @@ static void northbridge_topology_init(void) reg32 &= ~(0xffff << 16); reg32 |= 1 | (2 << 16); DMIBAR32(DMILE1D) = reg32; - DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; + DMIBAR32(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; + DMIBAR32(DMILE1A + 4) = 0; - DMIBAR64(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE; + DMIBAR32(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE; + DMIBAR32(DMILE2A + 4) = 0; reg32 = DMIBAR32(DMILE2D); reg32 &= ~(0xff << 16); reg32 |= 1 | (1 << 16); |