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authorElyes Haouas <ehaouas@noos.fr>2024-05-06 05:11:28 +0200
committerElyes Haouas <ehaouas@noos.fr>2024-05-07 10:52:44 +0000
commit78ba7a7865ed1f60c7f55bfcced305bc8fbdc9c6 (patch)
tree876ce8b879c63c3a121701047d35346388192176 /src/northbridge
parent0f3316bc71aab50dbd8464ee2fb5b680947f2ca5 (diff)
device/dram/ddr{3,4}: Rename spd_raw_data for specific DDR
Rename different spd_raw_data[] for DDR3 and DDR4. This is to solve the conflict when we include both "ddr3.h" and ddr4.h" for example here: src/device/dram/spd.c. Otherwise, it won't compile as DDR3 and DDR4 have different spd_raw_data[] size. Change-Id: I46597fe82790410fbb53d60e04b7fdffb7b0094a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/native_raminit/raminit_native.h2
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c14
2 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 1a0793947e..2a168666ac 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -33,7 +33,7 @@ enum generic_stepping {
};
struct raminit_dimm_info {
- spd_raw_data raw_spd;
+ spd_ddr3_raw_data raw_spd;
struct dimm_attr_ddr3_st data;
uint8_t spd_addr;
bool valid;
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 2b59b9e6af..2a4eae5bd5 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -123,7 +123,7 @@ static void setup_sdram_meminfo(ramctr_timing *ctrl)
}
/* Return CRC16 match for all SPDs */
-static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
+static int verify_crc16_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl)
{
int channel, slot, spd_slot;
int match = 1;
@@ -132,13 +132,13 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
for (slot = 0; slot < NUM_SLOTS; slot++) {
spd_slot = 2 * channel + slot;
match &= ctrl->spd_crc[channel][slot] ==
- spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
+ spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data));
}
}
return match;
}
-static void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
+static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only)
{
int j;
if (id_only) {
@@ -150,7 +150,7 @@ static void read_spd(spd_raw_data *spd, u8 addr, bool id_only)
}
}
-static void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+static void mainboard_get_spd(spd_ddr3_raw_data *spd, bool id_only)
{
const struct northbridge_intel_sandybridge_config *cfg = config_of_soc();
unsigned int i;
@@ -192,7 +192,7 @@ static void mainboard_get_spd(spd_raw_data *spd, bool id_only)
} /* CONFIG(HAVE_SPD_IN_CBFS) */
}
-static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
+static void dram_find_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl)
{
int dimms = 0, ch_dimms;
int channel, slot, spd_slot;
@@ -254,7 +254,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
/* Fill in CRC16 for MRC cache */
ctrl->spd_crc[channel][slot] =
- spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
+ spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data));
if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
/* Mark DIMM as invalid */
@@ -339,7 +339,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
{
int me_uma_size, cbmem_was_inited, fast_boot, err;
ramctr_timing ctrl;
- spd_raw_data spds[4];
+ spd_ddr3_raw_data spds[4];
size_t mrc_size;
ramctr_timing *ctrl_cached = NULL;