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authorFelix Held <felix-coreboot@felixheld.de>2021-04-09 22:22:09 +0200
committerPatrick Georgi <pgeorgi@google.com>2021-04-11 21:06:29 +0000
commit70d1c723f77608ba9c4295f5eb83d17c776f826b (patch)
treeaf8aa04f765ed40d4a669e37069c3d3937162c5c /src/northbridge
parentdfd9a62a90e90b8ed3d605e44525bbd736b0dbf9 (diff)
sb/amd/pi/hudson: remove unused Bolton PI FCH code
There is no nb/amd/pi northbridge left in coreboot that could be paired with the Bolton FCH, since the remaining nb/amd/pi northbridges all use an integrated FCH (Avalon on Mullins and Kern on Carrizo) while Bolton is a discrete FCH. I ran into this when verifying if the common soc/amd GPIO functionality that gets added by selecting SOC_AMD_COMMON_BLOCK_BANKED_GPIOS is valid for all chips selecting it and that code isn't valid for Bolton that uses the old GPIO 100 interface. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iffe876bee96e42645e1be10730b78959b1c06d59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52222 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/agesa/state_machine.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h
index a857727a0a..d88c459400 100644
--- a/src/northbridge/amd/agesa/state_machine.h
+++ b/src/northbridge/amd/agesa/state_machine.h
@@ -90,7 +90,6 @@ void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save);
CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) || \
CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \
CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || \
- CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON) || \
CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
#if HAS_AGESA_FCH_OEM_CALLOUT