diff options
| author | Nico Huber <nico.huber@secunet.com> | 2016-10-08 18:42:46 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2016-10-11 11:37:10 +0200 |
| commit | 6f8b7df8ab69cd2be7d024dfbd7fbeb3a684c6b3 (patch) | |
| tree | 3060c73ee0303ecb638fc9d80ce5268010855504 /src/northbridge | |
| parent | c9848a82e23f826adb97a251031b0625e9809b24 (diff) | |
cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZE
An epic battle to fix Nehalem finally ended when we found an odd mask
set in SMRR. This was caused by a wrong calculation of TSEG size. It
was assumed that TSEG spans the whole space between TSEG base
and GTT. This is wrong as TSEG base might have been aligned down.
TEST: On X201, copied 1GiB from usb key to sd-card and verified.
Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7
Found-by: Alexander Couzens, Nico Huber
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16939
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/northbridge.c | 11 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/northbridge.c | 11 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 11 |
3 files changed, 9 insertions, 24 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 99d8fbbcf4..50615b5f2d 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -325,16 +325,11 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -void -northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size) +u32 northbridge_get_tseg_base(void) { - device_t dev; - u32 bgsm; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - *tsegmb = northbridge_get_base_reg(dev, TSEG); - bgsm = northbridge_get_base_reg(dev, BGSM); - *tseg_size = bgsm - *tsegmb; + return northbridge_get_base_reg(dev, TSEG); } void northbridge_write_smram(u8 smram) diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 7f44272593..06c0a9655b 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -162,16 +162,11 @@ static void mc_read_resources(device_t dev) add_fixed_resources(dev, 10); } -void -northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size) +u32 northbridge_get_tseg_base(void) { - device_t dev; - u32 bgsm; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - *tsegmb = pci_read_config32(dev, TSEG) & ~1; - bgsm = pci_read_config32(dev, D0F0_GTT_BASE); - *tseg_size = bgsm - *tsegmb; + return pci_read_config32(dev, TSEG) & ~1; } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 53d93a2501..a67b84ddf4 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -500,16 +500,11 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) return value; } -void -northbridge_get_tseg_base_and_size(u32 *tsegmb, u32 *tseg_size) +u32 northbridge_get_tseg_base(void) { - device_t dev; - u32 bgsm; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - *tsegmb = northbridge_get_base_reg(dev, TSEG); - bgsm = northbridge_get_base_reg(dev, BGSM); - *tseg_size = bgsm - *tsegmb; + return northbridge_get_base_reg(dev, TSEG); } void northbridge_write_smram(u8 smram) |