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authorStefan Reinauer <stefan.reinauer@coreboot.org>2015-07-13 09:39:15 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-07-13 21:04:56 +0200
commit6cb3a59fd5e754c3627b79db21c5bcc284bfd721 (patch)
treee83db5b11ee4a29d496dcf2798d024b6b8455ab7 /src/northbridge
parent9693885ad88d21ead7bd9ebc32f3e4901841b18b (diff)
x86: flatten hierarchy
It never made sense to have bootblock_* in init, but pirq_routing.c in boot, and some ld scripts on the main level while others live in subdirectories. This patch flattens the directory hierarchy and makes x86 more similar to the other architectures. Change-Id: I4056038fe7813e4d3d3042c441e7ab6076a36384 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/10901 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/fsp_rangeley/Makefile.inc2
-rw-r--r--src/northbridge/intel/fsp_sandybridge/Makefile.inc2
-rw-r--r--src/northbridge/intel/haswell/Makefile.inc2
-rw-r--r--src/northbridge/intel/nehalem/Makefile.inc2
-rw-r--r--src/northbridge/intel/sandybridge/Makefile.inc2
5 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/fsp_rangeley/Makefile.inc b/src/northbridge/intel/fsp_rangeley/Makefile.inc
index eaa1a77e88..3b88913452 100644
--- a/src/northbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/northbridge/intel/fsp_rangeley/Makefile.inc
@@ -28,7 +28,7 @@ ramstage-y += acpi.c
ramstage-y += port_access.c
romstage-y += raminit.c
-romstage-y += ../../../arch/x86/lib/walkcbfs.S
+romstage-y += ../../../arch/x86/walkcbfs.S
romstage-y += port_access.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
index 42c16fa6ca..6c5e09f9b4 100644
--- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc
+++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc
@@ -31,7 +31,7 @@ romstage-y += raminit.c
romstage-y += ram_calc.c
romstage-y += early_init.c
romstage-y += report_platform.c
-romstage-y += ../../../arch/x86/lib/walkcbfs.S
+romstage-y += ../../../arch/x86/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 330dc00b91..ad4b2ba2f3 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -32,7 +32,7 @@ romstage-y += raminit.c
romstage-y += mrccache.c
romstage-y += early_init.c
romstage-y += report_platform.c
-romstage-y += ../../../arch/x86/lib/walkcbfs.S
+romstage-y += ../../../arch/x86/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index cb02fd8a68..e5b4385ea9 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -31,7 +31,7 @@ romstage-y += ram_calc.c
romstage-y += raminit.c
romstage-y += early_init.c
romstage-y += ../sandybridge/mrccache.c
-romstage-y += ../../../arch/x86/lib/walkcbfs.S
+romstage-y += ../../../arch/x86/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index cf79459df2..407b61d8a7 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -40,7 +40,7 @@ romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += ../../../device/dram/
romstage-y += mrccache.c
romstage-y += early_init.c
romstage-y += report_platform.c
-romstage-y += ../../../arch/x86/lib/walkcbfs.S
+romstage-y += ../../../arch/x86/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c