diff options
| author | Florian Zumbiehl <florz@florz.de> | 2011-12-10 19:39:49 +0100 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2011-12-14 08:50:45 +0100 |
| commit | 36b53bf2445f85cd89711de37e4123f761478afe (patch) | |
| tree | a865d069a4e5ee99dc82a6ff2bbd74b034ef974b /src/northbridge | |
| parent | 20d9de33ccb71d3cd233f77f244af4e53c8846ca (diff) | |
k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/481
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/Kconfig | 6 | ||||
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit.c | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a061..70e75e9007 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -37,6 +37,12 @@ config MEM_TRAIN_SEQ int default 0 +# Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and +# single DIMM is indeed unreliable without it). +config K8_FORCE_2T_DRAM_TIMING + bool + default n + config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 98044d483e..eb33a39745 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1477,7 +1477,7 @@ hw_error: if (dloading != 0) { /* we have valid combination check the restrictions */ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); - dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T) : 0; + dcl |= ((dimm_loading_config[dpos][rpos] & DDR_2T) || CONFIG_K8_FORCE_2T_DRAM_TIMING) ? (DCL_En2T) : 0; /* Set DuallDimm is second channel is completely empty (revD+) */ if (((cpuid_eax(1) & 0xfff0f) >= 0x10f00) && ((dpos & 0x5) == 0)) { printk(BIOS_DEBUG, "Setting DualDIMMen\n"); @@ -1661,7 +1661,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * goto hw_error; #if CONFIG_CPU_AMD_SOCKET_754 - if (freq < max_freq_1t) { + if (freq < max_freq_1t || CONFIG_K8_FORCE_2T_DRAM_TIMING) { pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) | DCL_En2T); } |