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authorAngel Pons <th3fanbus@gmail.com>2020-09-14 18:58:53 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-09-17 19:59:29 +0000
commit298d34d8ffae14fb5fe154dc6c5e7abfa69a7061 (patch)
tree1d8c3653a2a48551b1e07893dd5082d6045d2ec0 /src/northbridge
parent8690746efbbeec846c52e31b31252837c4684b20 (diff)
nb/intel/ironlake: Do not re-read ME UMA size
It has been read twice already, so don't read it a third time. Change-Id: I56ec3a10246f6ebe8074e7b8c164bda6b90eee87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/ironlake/raminit.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 4d2e77a012..7263e2e846 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -1805,15 +1805,10 @@ static void send_heci_uma_message(struct raminfo *info)
static void setup_heci_uma(struct raminfo *info)
{
- u32 reg44;
-
- reg44 = pci_read_config32(HECIDEV, 0x44); // = 0x80010020
- info->memory_reserved_for_heci_mb = 0;
info->heci_uma_addr = 0;
- if (!((reg44 & 0x10000) && !(pci_read_config32(HECIDEV, 0x40) & 0x20)))
+ if (!info->memory_reserved_for_heci_mb && !(pci_read_config32(HECIDEV, 0x40) & 0x20))
return;
- info->memory_reserved_for_heci_mb = reg44 & 0x3f;
info->heci_uma_addr =
((u64)
((((u64) pci_read_config16(NORTHBRIDGE, TOM)) << 6) -