diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-17 20:43:41 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-20 17:16:30 +0200 |
| commit | 2051448359e3e7cbccf63f1817fa14468dcd50c8 (patch) | |
| tree | 5b6cea5da227e7913c4f78cd3ba8ef87cb5109d9 /src/northbridge | |
| parent | 9a9c8dba8ddd549d0d6dd23d3a194ffcf427afad (diff) | |
northbridge/intel/fsp_sandybridge: Add space around operators
Change-Id: I1b5cdfaf39be639a7ef71e66e91284fa186fbb86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16630
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
5 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c index 4da51577b6..499d96fef2 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ b/src/northbridge/intel/fsp_sandybridge/acpi.c @@ -41,7 +41,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) if (!dev) return current; - pciexbar_reg=pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = pci_read_config32(dev, PCIEXBAR); // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl index 90d1b1afa8..dfe5e257af 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl @@ -134,7 +134,7 @@ Device (MCHC) } /* - * Search CPU0 _PSS looking for control=arg0 and then + * Search CPU0 _PSS looking for control = arg0 and then * return previous P-state entry number for new _PPC * * Format of _PSS: diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index 08c3b0cf42..888da8ee14 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -95,7 +95,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { - *(void **)CBMEM_FSP_HOB_PTR=HobListPtr; + *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; if (Status == 0xFFFFFFFF) { hard_reset(); } diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index a33cafa226..cda9e08482 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -31,7 +31,7 @@ u32 map_oprom_vendev(u32 vendev) { - u32 new_vendev=vendev; + u32 new_vendev = vendev; switch (vendev) { case 0x80860102: /* GT1 Desktop */ @@ -41,7 +41,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x80860122: /* GT2 Desktop >=1.3GHz */ case 0x80860126: /* GT2 Mobile >=1.3GHz */ case 0x80860166: /* IVB */ - new_vendev=0x80860106; /* GT1 Mobile */ + new_vendev = 0x80860106; /* GT1 Mobile */ break; } diff --git a/src/northbridge/intel/fsp_sandybridge/udelay.c b/src/northbridge/intel/fsp_sandybridge/udelay.c index d4821999d5..8f95595c12 100644 --- a/src/northbridge/intel/fsp_sandybridge/udelay.c +++ b/src/northbridge/intel/fsp_sandybridge/udelay.c @@ -19,7 +19,7 @@ #include <cpu/x86/msr.h> /** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz + * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK = 100MHz */ void udelay(u32 us) |