via: Start template for VIA C7 w/ CX700 northbridge

The first steps to bring C7 and CX700 support back mainline. Most is
skeleton copied from the `min86' example.

The romstage entry is placed in the northbridge code, as that's where
we'll perform raminit. Support to read the FSB frequency is added right
away, same for a reset function (using CF9 reset), as both are required
for a minimal build test.

A mainboard VIA EPIA-EX is also introduced for build testing, and in
later stages boot testing as well.

Links:
DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b172d347554179891.pdf
PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221

Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 101 insertions, 0 deletions

diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig
new file mode 100644
index 0000000000..95f289aacb
--- /dev/null
+++ b/src/northbridge/via/cx700/Kconfig
@@ -0,0 +1,14 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config NORTHBRIDGE_VIA_CX700
+	bool
+	select PCI
+	select NO_ECAM_MMCONF_SUPPORT
+	select HAVE_CF9_RESET
+
+if NORTHBRIDGE_VIA_CX700
+
+config CHIPSET_DEVICETREE
+	default "northbridge/via/cx700/chipset.cb"
+
+endif
diff --git a/src/northbridge/via/cx700/Makefile.mk b/src/northbridge/via/cx700/Makefile.mk
new file mode 100644
index 0000000000..550ee2dec3
--- /dev/null
+++ b/src/northbridge/via/cx700/Makefile.mk
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ifeq ($(CONFIG_NORTHBRIDGE_VIA_CX700),y)
+
+romstage-y	+= romstage.c
+ramstage-y	+= chip.c
+all-y		+= clock.c reset.c
+
+endif
diff --git a/src/northbridge/via/cx700/chip.c b/src/northbridge/via/cx700/chip.c
new file mode 100644
index 0000000000..57583b84c7
--- /dev/null
+++ b/src/northbridge/via/cx700/chip.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+
+struct chip_operations northbridge_via_cx700_ops = { NULL };
diff --git a/src/northbridge/via/cx700/chipset.cb b/src/northbridge/via/cx700/chipset.cb
new file mode 100644
index 0000000000..4dd11f307e
--- /dev/null
+++ b/src/northbridge/via/cx700/chipset.cb
@@ -0,0 +1,17 @@
+chip northbridge/via/cx700
+
+	device domain 0 on
+
+		device pci 00.0 alias host_ctrl	on  end
+		device pci 00.1 alias host_err	on  end
+		device pci 00.2 alias host_if	on  end
+		device pci 00.3 alias dram_ctrl	on  end
+		device pci 00.4 alias pm_ctrl	on  end
+		device pci 00.7 alias north_end	on  end
+		device pci 01.0 alias north_pci	off
+			device pci 00.0 alias vga off end
+		end
+
+	end
+
+end
diff --git a/src/northbridge/via/cx700/clock.c b/src/northbridge/via/cx700/clock.c
new file mode 100644
index 0000000000..6bd5942a93
--- /dev/null
+++ b/src/northbridge/via/cx700/clock.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define __SIMPLE_DEVICE__
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <static_devices.h>
+#include <delay.h>
+
+static unsigned int read_timer_fsb(void)
+{
+	/* Allows access to all northbridge PCI devfn's */
+	pci_write_config8(_sdev_host_ctrl, 0x4f, 0x01);
+
+	const u8 misc_1 = pci_read_config8(_sdev_host_if, 0x54);
+	switch (misc_1 >> 5) {
+	case 0:
+		return 100;
+	case 1:
+		return 133;
+	case 2:
+		return 166;
+	case 3:
+		return 200;
+	default:
+		printk(BIOS_WARNING, "Unknown FSB frequency encoding: 0x%x\n", misc_1 >> 5);
+		return 200;
+	}
+}
+
+u32 get_timer_fsb(void)
+{
+	static unsigned int fsb_mhz;
+
+	if (!fsb_mhz)
+		fsb_mhz = read_timer_fsb();
+
+	return fsb_mhz;
+}
diff --git a/src/northbridge/via/cx700/reset.c b/src/northbridge/via/cx700/reset.c
new file mode 100644
index 0000000000..b052f1d8d5
--- /dev/null
+++ b/src/northbridge/via/cx700/reset.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <reset.h>
+#include <cf9_reset.h>
+
+void do_board_reset(void)
+{
+	full_reset();
+}
diff --git a/src/northbridge/via/cx700/romstage.c b/src/northbridge/via/cx700/romstage.c
new file mode 100644
index 0000000000..f4c5584c30
--- /dev/null
+++ b/src/northbridge/via/cx700/romstage.c
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <romstage_common.h>
+#include <halt.h>
+
+void __noreturn romstage_main(void)
+{
+	/* Needed for __noreturn */
+	halt();
+}