diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-11-15 22:10:26 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-17 16:27:43 +0000 |
| commit | 0010b89c67354dd4dda1417e6fc990cc3b82f0d4 (patch) | |
| tree | 471d72f3718e07bdd297e00eb4daf9bd0421e83b /src/northbridge | |
| parent | 10e478c4cf31e09326065e1126222b49d01eb6fa (diff) | |
nb/amd/pi/00730F01: introduce and use chipset devicetree
BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI
devices. The HDA controller in the FCH at function 2 of device 0x14 on
bus 0 was missing in the mainboard's devicetrees.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/Kconfig | 4 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/chipset.cb | 40 |
2 files changed, 44 insertions, 0 deletions
diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 651735a5c9..493bc6a13e 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -6,6 +6,10 @@ config NORTHBRIDGE_AMD_PI_00730F01 if NORTHBRIDGE_AMD_PI_00730F01 +config CHIPSET_DEVICETREE + string + default "northbridge/amd/pi/00730F01/chipset.cb" + config HW_MEM_HOLE_SIZEK hex default 0x100000 diff --git a/src/northbridge/amd/pi/00730F01/chipset.cb b/src/northbridge/amd/pi/00730F01/chipset.cb new file mode 100644 index 0000000000..2ddfcebbf4 --- /dev/null +++ b/src/northbridge/amd/pi/00730F01/chipset.cb @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/pi/00730F01/root_complex + device cpu_cluster 0 on end + + device domain 0 on + chip northbridge/amd/pi/00730F01 + device pci 0.0 alias gnb on end + device pci 0.2 alias iommu off end + device pci 1.0 alias gfx off end + device pci 1.1 alias gfx_hda off end + device pci 2.0 on end # Dummy Host Bridge, do not disable + device pci 2.1 alias gpp_bridge_0 off end + device pci 2.2 alias gpp_bridge_1 off end + device pci 2.3 alias gpp_bridge_2 off end + device pci 2.4 alias gpp_bridge_3 off end + device pci 2.5 alias gpp_bridge_4 off end + device pci 8.0 alias psp on end + end + + chip southbridge/amd/pi/hudson + device pci 10.0 alias xhci off end + device pci 11.0 alias sata off end + device pci 12.0 alias ehci_0 off end + device pci 13.0 alias ehci_1 off end + device pci 14.0 alias smbus on end + device pci 14.2 alias hda off end + device pci 14.3 alias lpc_bridge on end + device pci 14.7 alias sdhci off end + device pci 16.0 alias ehci_2 off end + end + + device pci 18.0 alias ht_0 on end + device pci 18.1 alias ht_1 on end + device pci 18.2 alias ht_2 on end + device pci 18.3 alias ht_3 on end + device pci 18.4 alias ht_4 on end + device pci 18.5 alias ht_5 on end + end +end |