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authorRonald G. Minnich <rminnich@gmail.com>2003-08-04 22:13:57 +0000
committerRonald G. Minnich <rminnich@gmail.com>2003-08-04 22:13:57 +0000
commit60e185fcc4f2cfe1f8c01011ab976c10b2975f7a (patch)
tree7ba6a027aec89e3d931cf098db914fbf9580034c /src/northbridge
parenta43048d371ad4bfaa7a53b3621770907b5d1879d (diff)
patches from Yh Lu. Tested and working on HDAMA
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdk8/raminit.c20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index df0eebe7c6..63a471c870 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1124,6 +1124,23 @@ static void spd_set_ram_size(const struct mem_controller *ctrl)
}
}
+//BY LYH //Fill next base reg with right value
+static void fill_last(unsigned long node_id,unsigned long base)
+{
+ unsigned i;
+ unsigned base_reg;
+ base &=0xffff0000;
+ device_t device;
+ for(device = PCI_DEV(0, 0x18, 1); device <= PCI_DEV(0, 0x1f, 1); device
++= PCI_DEV(0, 1, 0)) {
+ for(i=node_id+1;i<=7;i++) {
+ base_reg=0x40+(i<<3);
+ pci_write_config32(device,base_reg,base);
+ }
+ }
+}
+//BY LYH END
+
static void route_dram_accesses(const struct mem_controller *ctrl,
unsigned long base_k, unsigned long limit_k)
{
@@ -1276,6 +1293,9 @@ static void order_dimms(const struct mem_controller *ctrl)
print_debug("\r\n");
#endif
route_dram_accesses(ctrl, base_k, tom_k);
+//BY LYH
+ fill_last(ctrl->node_id, tom_k<<2);
+//BY LYH END
set_top_mem(tom_k);
}