diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-06-15 20:28:32 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-20 22:00:40 +0200 |
| commit | 55409ebbb65cd52c4f5c47f0c1232e8bef0cc4a3 (patch) | |
| tree | 3f84897c8ac730e8868c2f0ca051c4880a5d46cd /src/northbridge | |
| parent | d4c53e3fdd29612641ae402b57495401e67a414e (diff) | |
nb/intel/sandybridge/raminit: Use supported CAS
Instead of programming unsupported CAS use the highest supported
value. Start at DDR3 maximum of CAS 18T.
Increase error message verbosity level.
Useful for overclocking.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Allows to run a DDR3-1600 DIMM at 933Mhz.
Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15217
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index ba03bbbc92..cf66a0d54c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -722,8 +722,16 @@ static void dram_timing(ramctr_timing * ctrl) val++; } /* Is CAS supported */ - if (!(ctrl->cas_supported & (1 << (val - 4)))) - printk(BIOS_DEBUG, "CAS not supported\n"); + if (!(ctrl->cas_supported & (1 << (val - 4)))) { + printk(BIOS_ERR, "CAS %uT not supported. ", val); + val = 18; + /* Find highest supported CAS latency */ + while (!((ctrl->cas_supported >> (val - 4)) & 1)) + val--; + + printk(BIOS_ERR, "Using CAS %uT instead.\n", val); + } + printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); ctrl->CAS = val; ctrl->CWL = get_CWL(ctrl->CAS); |