Clean up Geode GX2 comments, whitespace and coding style. Trivial.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 128 insertions, 148 deletions

diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c
index e59a838afe..6c043fe662 100644
--- a/src/northbridge/amd/gx2/grphinit.c
+++ b/src/northbridge/amd/gx2/grphinit.c
@@ -5,13 +5,10 @@
 #include "chip.h"
 #include "northbridge.h"
 
-// FIXME handle UMA properly.
-#define VIDEO_MB	8					// MB of video memory
+/* FIXME handle UMA properly. */
+#define VIDEO_MB	8	/* MB of video memory */
 
-
- /*
- * This function mirrors the Graphics_Init routine in GeodeROM.
- */
+/* This function mirrors the Graphics_Init routine in GeodeROM. */
 void graphics_init(void)
 {
 	/* SoftVG initialization */
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index 987ebabfef..2b1db0d892 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -20,15 +20,15 @@
 #define NORTHBRIDGE_FILE "northbridge.c"
 
 /* todo: add a resource record. We don't do this here because this may be called when
-  * very little of the platform is actually working.
-  */
-int
-sizeram(void)
+ * very little of the platform is actually working.
+ */
+int sizeram(void)
 {
 	msr_t msr;
 	int sizem = 0;
 	unsigned short dimm;
 
+	/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
 	msr = rdmsr(0x20000018);
 	printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
 
@@ -38,8 +38,7 @@ sizeram(void)
 	if ((dimm & 7) != 7)
 		sizem = (1 << ((dimm >> 12)-1)) * 8;
 
-
-	/* dimm 1*/
+	/* dimm 1 */
 	dimm = msr.hi >> 16;
 	/* installed? */
 	if ((dimm & 7) != 7)
@@ -49,8 +48,7 @@ sizeram(void)
 	return sizem;
 }
 
-
-/* here is programming for the various MSRs.*/
+/* here is programming for the various MSRs. */
 #define IM_QWAIT 0x100000
 
 #define DMCF_WRITE_SERIALIZE_REQUEST (2<<12) /* 2 outstanding */ /* in high */
@@ -86,9 +84,8 @@ sizeram(void)
 #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
 #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
 
-
-
-struct msr_defaults {
+struct msr_defaults
+{
 	int msr_no;
 	msr_t msr;
 } msr_defaults [] = {
@@ -121,7 +118,8 @@ struct msr_defaults {
 };
 
 /* note that dev is NOT used -- yet */
-static void irq_init_steering(struct device *dev, u16 irq_map) {
+static void irq_init_steering(struct device *dev, u16 irq_map)
+{
 	/* Set up IRQ steering */
 	u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
 
@@ -142,16 +140,12 @@ static void irq_init_steering(struct device *dev, u16 irq_map) {
 	outl(irq_map,      0xCFC);
 }
 
-
-/*
- * setup_gx2_cache
+/* setup_gx2_cache
  *
  * Returns the amount of memory (in KB) available to the system.  This is the
  * total amount of memory less the amount of memory reserved for SMM use.
- *
  */
-static int
-setup_gx2_cache(void)
+static int setup_gx2_cache(void)
 {
 	msr_t msr;
 	unsigned long long val;
@@ -164,7 +158,7 @@ setup_gx2_cache(void)
 	/* set romrp */
 	val = ((unsigned long long) ROM_PROPERTIES) << 56;
 	/* make rom base useful for 1M roms */
-	/* Flash base address -- sized for 1M for now*/
+	/* Flash base address -- sized for 1M for now */
 	val |= ((unsigned long long) 0xfff00)<<36;
 	/* set the devrp properties */
 	val |= ((unsigned long long) DEVICE_PROPERTIES) << 28;
@@ -172,7 +166,7 @@ setup_gx2_cache(void)
 	/* yank off memory for the SMM handler */
 	sizekbytes -= SMM_SIZE;
 	sizereg = sizekbytes;
-	sizereg *= 1024;	// convert to bytes
+	sizereg *= 1024;	/* convert to bytes */
 	sizereg >>= 12;
 	sizereg <<= 8;
 	val |= sizereg;
@@ -188,10 +182,8 @@ setup_gx2_cache(void)
 }
 
 /* we have to do this here. We have not found a nicer way to do it */
-static void
-setup_gx2(void)
+static void setup_gx2(void)
 {
-
 	unsigned long tmp, tmp2;
 	msr_t msr;
 	unsigned long size_kb, membytes;
@@ -200,13 +192,13 @@ setup_gx2(void)
 
 	membytes = size_kb * 1024;
 	/* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
-	  * so it is safe to use. You should NOT at this point call
-	  * sizeram() directly.
-	  */
+	 * so it is safe to use. You should NOT at this point call
+	 * sizeram() directly.
+	 */
 
 	/* we need to set 0x10000028 and 0x40000029 */
-	/*
-	 * These two descriptors cover the range from 1 MB (0x100000) to
+
+	/* These two descriptors cover the range from 1 MB (0x100000) to
 	 * SYSTOP (a.k.a. TOM, or Top of Memory)
 	 */
 
@@ -258,11 +250,11 @@ setup_gx2(void)
 	msr = rdmsr(0x1808);
 	printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
 #endif
-#if 0	// SDG - don't do this
+#if 0	/* SDG - don't do this */
 	/* now do the default MSR values */
 	for(i = 0; msr_defaults[i].msr_no; i++) {
 		msr_t msr;
-		wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);	// MSR - see table above
+		wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr);	/* MSR - see table above */
 		msr = rdmsr(msr_defaults[i].msr_no);
 		printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
 	}
@@ -297,51 +289,49 @@ static void northbridge_init(device_t dev)
 static void set_resources(struct device *dev)
 {
 #if 0
-        struct resource *res;
+	struct resource *res;
 
-        for(res = &dev->resource_list; res; res = res->next) {
-                pci_set_resource(dev, resource);
-        }
+	for(res = &dev->resource_list; res; res = res->next) {
+		pci_set_resource(dev, resource);
+	}
 #endif
 	struct bus *bus;
 
 	for(bus = dev->link_list; bus; bus = bus->next) {
-                if (bus->children) {
-                        assign_resources(bus);
-                }
-        }
+		if (bus->children) {
+			assign_resources(bus);
+		}
+	}
 
 #if 0
-        /* set a default latency timer */
-        pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
-
-        /* set a default secondary latency timer */
-        if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
-                pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
-        }
-
-        /* zero the irq settings */
-        u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
-        if (line) {
-                pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
-        }
-        /* set the cache line size, so far 64 bytes is good for everyone */
-        pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
-#endif
-}
+	/* set a default latency timer */
+	pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
 
+	/* set a default secondary latency timer */
+	if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
+		pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
+	}
 
+	/* zero the irq settings */
+	u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+	if (line) {
+		pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
+	}
+	/* set the cache line size, so far 64 bytes is good for everyone */
+	pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
+#endif
+}
 
 static struct device_operations northbridge_operations = {
-	.read_resources   = pci_dev_read_resources,
+	.read_resources = pci_dev_read_resources,
 #if 0
-	.set_resources    = pci_dev_set_resources,
+	.set_resources = pci_dev_set_resources,
 #endif
-	.set_resources    = set_resources,
+	.set_resources = set_resources,
 	.enable_resources = pci_dev_enable_resources,
-	.init             = northbridge_init,
-	.enable           = 0,
-	.ops_pci          = 0,
+	.init = northbridge_init,
+	.enable = 0,
+	.ops_pci = 0,
 };
 
 static const struct pci_driver northbridge_driver __pci_driver = {
@@ -350,16 +340,16 @@ static const struct pci_driver northbridge_driver __pci_driver = {
 	.device = PCI_DEVICE_ID_NS_GX2,
 };
 
-// FIXME handle UMA correctly.
+/* FIXME handle UMA correctly. */
 #define FRAMEBUFFERK 4096
 
 static void pci_domain_set_resources(device_t dev)
 {
 #if 0
 	device_t mc_dev;
-        u32 pci_tolm;
+	u32 pci_tolm;
 
-        pci_tolm = find_pci_tolm(dev->link_list);
+	pci_tolm = find_pci_tolm(dev->link_list);
 	mc_dev = dev->link_list->children;
 	if (mc_dev) {
 		unsigned int tomk, tolmk;
@@ -405,16 +395,16 @@ static void pci_domain_set_resources(device_t dev)
 }
 
 static struct device_operations pci_domain_ops = {
-        .read_resources   = pci_domain_read_resources,
-        .set_resources    = pci_domain_set_resources,
-        .enable_resources = NULL,
-        .init             = NULL,
-        .scan_bus         = pci_domain_scan_bus,
+	.read_resources = pci_domain_read_resources,
+	.set_resources = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init = NULL,
+	.scan_bus = pci_domain_scan_bus,
 };
 
 static void cpu_bus_init(device_t dev)
 {
-        initialize_cpus(dev->link_list);
+	initialize_cpus(dev->link_list);
 }
 
 static void cpu_bus_noop(device_t dev)
@@ -422,11 +412,11 @@ static void cpu_bus_noop(device_t dev)
 }
 
 static struct device_operations cpu_bus_ops = {
-        .read_resources   = cpu_bus_noop,
-        .set_resources    = cpu_bus_noop,
-        .enable_resources = cpu_bus_noop,
-        .init             = cpu_bus_init,
-        .scan_bus         = 0,
+	.read_resources = cpu_bus_noop,
+	.set_resources = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init = cpu_bus_init,
+	.scan_bus = 0,
 };
 
 void chipsetInit (void);
@@ -440,8 +430,8 @@ static void enable_dev(struct device *dev)
 	printk(BIOS_DEBUG, "gx2 north: enable_dev\n");
 	void do_vsmbios(void);
 
-        /* Set the operations if it is a special bus type */
-        if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 		u32 tomk;
 		printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
 		/* cpubug MUST be called before setup_gx2(), so we force the issue here */
@@ -460,10 +450,10 @@ static void enable_dev(struct device *dev)
 		high_tables_size = HIGH_MEMORY_SIZE;
 #endif
 		ram_resource(dev, 0, 0, tomk);
-        } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 		printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n");
-                dev->ops = &cpu_bus_ops;
-        }
+		dev->ops = &cpu_bus_ops;
+	}
 	printk(BIOS_DEBUG, "gx2 north: end enable_dev\n");
 }
 
diff --git a/src/northbridge/amd/gx2/northbridgeinit.c b/src/northbridge/amd/gx2/northbridgeinit.c
index 410998a70f..446c1e79cf 100644
--- a/src/northbridge/amd/gx2/northbridgeinit.c
+++ b/src/northbridge/amd/gx2/northbridgeinit.c
@@ -15,38 +15,40 @@
 
 /* put this here for now, we are not sure where it belongs */
 
-struct gliutable {
+struct gliutable
+{
 	unsigned long desc_name;
 	unsigned short desc_type;
 	unsigned long hi, lo;
 };
 
 struct gliutable gliu0table[] = {
-	{.desc_name=MSR_GLIU0_BASE1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},		/* 0-7FFFF to MC */
+	{.desc_name=MSR_GLIU0_BASE1,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=  0x0FFF80},			/* 0-7FFFF to MC */
 	{.desc_name=MSR_GLIU0_BASE2,  .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0},	/* 80000-9ffff to Mc */
-	{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},	/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
-	{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},		/* Catch and fix dynamicly. */
-	{.desc_name=MSR_GLIU0_DMM,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},		/* Catch and fix dynamicly. */
-	{.desc_name=MSR_GLIU0_SMM,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},		/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi=  MSR_MC + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
+	{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU0_DMM,    .desc_type= BMO_DMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU0_SMM,    .desc_type= BMO_SMM,.hi=  MSR_MC,.lo=  0x0},			/* Catch and fix dynamicly. */
 	{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
 	{.desc_name=GL_END,           .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
 struct gliutable gliu1table[] = {
-	{.desc_name=MSR_GLIU1_BASE1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},	/* 0-7FFFF to MC */
+	{.desc_name=MSR_GLIU1_BASE1,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo=  0x0FFF80},		/* 0-7FFFF to MC */
 	{.desc_name=MSR_GLIU1_BASE2,.desc_type=  BM,.hi=  MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0},	/* 80000-9ffff to Mc */
-	{.desc_name=MSR_GLIU1_SHADOW,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03},	/* C0000-Fffff split to MC and PCI (sub decode) */
-	{.desc_name=MSR_GLIU1_SYSMEM,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},		/* Catch and fix dynamicly. */
-	{.desc_name=MSR_GLIU1_DMM,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
-	{.desc_name=MSR_GLIU1_SMM,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU1_SHADOW,.desc_type=  SC_SHADOW,.hi=  MSR_GL0 + 0x0,.lo=  0x03},		/* C0000-Fffff split to MC and PCI (sub decode) */
+	{.desc_name=MSR_GLIU1_SYSMEM,.desc_type=  R_SYSMEM,.hi=  MSR_GL0,.lo=  0x0},			/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU1_DMM,.desc_type=  BM_DMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
+	{.desc_name=MSR_GLIU1_SMM,.desc_type=  BM_SMM,.hi=  MSR_GL0,.lo=  0x0},				/* Catch and fix dynamicly. */
 	{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
-	{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0},	/* FooGlue FPU 0xF0 */
+	{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type=  SCIO,.hi=  (GL1_GLCP << 29) + 0x0,.lo=  0x033000F0}, /* FooGlue FPU 0xF0 */
 	{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
 };
 
 struct gliutable *gliutables[]  = {gliu0table, gliu1table, 0};
 
-struct msrinit {
+struct msrinit
+{
 	unsigned long msrnum;
 	msr_t msr;
 };
@@ -56,15 +58,16 @@ struct msrinit ClockGatingDefault [] = {
 	/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
 	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},
 	{GLIU1_GLD_MSR_PM,	{.hi=0x00,.lo=0x0005}},
-	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},		/* lotus #77.163 */
+	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},	/* lotus #77.163 */
 	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
 	{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0155}},
 	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
 	{GLPCI_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
-	{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},		/* Always on */
+	{FG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},	/* Always on */
 	{0xffffffff, 				{0xffffffff, 0xffffffff}},
 };
-	/*  All On */
+
+/* All On */
 struct msrinit ClockGatingAllOn[] = {
 	{GLIU0_GLD_MSR_PM,	{.hi=0x00,.lo=0x0FFFFFFFF}},
 	{MC_GLD_MSR_PM,		{.hi=0x00,.lo=0x0FFFFFFFF}},
@@ -78,16 +81,16 @@ struct msrinit ClockGatingAllOn[] = {
  	{0xffffffff, 				{0xffffffff, 0xffffffff}},
 };
 
-	/* Performance */
+/* Performance */
 struct msrinit ClockGatingPerformance[] = {
-	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},		/*  lotus #77.163*/
+	{VG_GLD_MSR_PM,		{.hi=0x00,.lo=0x0000}},	/* lotus #77.163 */
 	{GP_GLD_MSR_PM,		{.hi=0x00,.lo=0x0001}},
 	{DF_GLD_MSR_PM,		{.hi=0x00,.lo=0x0155}},
 	{GLCP_GLD_MSR_PM,	{.hi=0x00,.lo=0x0015}},
 	{0xffffffff, 				{0xffffffff, 0xffffffff}},
 };
 
-	/* SET GeodeLink PRIORITY */
+/* SET GeodeLink PRIORITY */
 struct msrinit GeodeLinkPriorityTable [] = {
 	{CPU_GLD_MSR_CONFIG,		{.hi=0x00,.lo=0x0220}},		/* CPU Priority. */
 	{DF_GLD_MSR_MASTER_CONF,	{.hi=0x00,.lo=0x0000}},		/* DF Priority. */
@@ -103,8 +106,8 @@ struct msrinit GeodeLinkPriorityTable [] = {
 /* do we have dmi or not? assume NO per AMD */
 int havedmi = 0;
 
-static void
-writeglmsr(struct gliutable *gl){
+static void writeglmsr(struct gliutable *gl)
+{
 	msr_t msr;
 
 	msr.lo = gl->lo;
@@ -116,8 +119,7 @@ writeglmsr(struct gliutable *gl){
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
-static void
-ShadowInit(struct gliutable *gl)
+static void ShadowInit(struct gliutable *gl)
 {
 	msr_t msr;
 
@@ -132,14 +134,12 @@ ShadowInit(struct gliutable *gl)
  * CLEAN ME UP
  */
 /* yes, this duplicates later code, but it seems that is how they want it done. */
-static void
-SysmemInit(struct gliutable *gl)
+static void SysmemInit(struct gliutable *gl)
 {
 	msr_t msr;
 	int sizembytes, sizebytes;
 
-	/*
-	 * Figure out how much RAM is in the machine and alocate all to the
+	/* Figure out how much RAM is in the machine and alocate all to the
 	 * system. We will adjust for SMM and DMM now and Frame Buffer later.
 	 */
 	sizembytes = sizeram();
@@ -164,8 +164,8 @@ SysmemInit(struct gliutable *gl)
 				gl->desc_name, msr.hi, msr.lo);
 }
 
-static void
-DMMGL0Init(struct gliutable *gl) {
+static void DMMGL0Init(struct gliutable *gl)
+{
 	msr_t msr;
 	int sizebytes = sizeram()<<20;
 	long offset;
@@ -191,8 +191,8 @@ DMMGL0Init(struct gliutable *gl) {
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
-static void
-DMMGL1Init(struct gliutable *gl) {
+static void DMMGL1Init(struct gliutable *gl)
+{
 	msr_t msr;
 
 	if (! havedmi)
@@ -214,8 +214,8 @@ DMMGL1Init(struct gliutable *gl) {
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
-static void
-SMMGL0Init(struct gliutable *gl) {
+static void SMMGL0Init(struct gliutable *gl)
+{
 	msr_t msr;
 	int sizebytes = sizeram()<<20;
 	long offset;
@@ -242,8 +242,8 @@ SMMGL0Init(struct gliutable *gl) {
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
-static void
-SMMGL1Init(struct gliutable *gl) {
+static void SMMGL1Init(struct gliutable *gl)
+{
 	msr_t msr;
 	printk(BIOS_DEBUG, "%s:\n", __func__ );
 
@@ -259,9 +259,8 @@ SMMGL1Init(struct gliutable *gl) {
 	printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
 }
 
-static void
-GLIUInit(struct gliutable *gl){
-
+static void GLIUInit(struct gliutable *gl)
+{
 	while (gl->desc_type != GL_END){
 		switch(gl->desc_type){
 		default:
@@ -295,8 +294,7 @@ GLIUInit(struct gliutable *gl){
 	}
 }
 
-/*
- * Set up GLPCI settings for reads/write into memory.
+/* Set up GLPCI settings for reads/write into memory.
  *
  * R0:  0-640KB,
  * R1:  1MB - Top of System Memory
@@ -304,7 +302,8 @@ GLIUInit(struct gliutable *gl){
  * R3: Framebuffer? - not set up yet
  * R4: ??
  */
-static void GLPCIInit(void){
+static void GLPCIInit(void)
+{
 	struct gliutable *gl = 0;
 	int i;
 	msr_t msr;
@@ -334,7 +333,7 @@ static void GLPCIInit(void){
                  * base of 1M and top of around 256M
 		 */
 		/* we have to create a page-aligned (4KB page) address for base and top
-		 * So we need a high page aligned addresss (pah) and low page aligned address (pal)
+		 * so we need a high page aligned addresss (pah) and low page aligned address (pal)
 		 * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
 		 */
 		printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
@@ -504,8 +503,7 @@ static void GeodeLinkPriority(void)
 	}
 }
 
-/*
- * Get the GLIU0 shadow register settings.
+/* Get the GLIU0 shadow register settings.
  *
  * If the setShadow function is used then all shadow descriptors
  * will stay sync'ed.
@@ -517,8 +515,7 @@ static uint64_t getShadow(void)
 	return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
 }
 
-/*
- * Set the cache RConf registers for the memory hole.
+/* Set the cache RConf registers for the memory hole.
  *
  * Keeps all cache shadow descriptors sync'ed.
  * This is part of the PCI lockup solution.
@@ -536,17 +533,17 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
 	/* load up D000 settings in edx. */
 	for (bit = 8; (bit > 4); bit--) {
 		msr.hi <<= 8;
-		msr.hi |= 1;				/* cache disable PCI/Shadow memory */
+		msr.hi |= 1;			/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
-			msr.hi |= 0x20;			/* write serialize PCI memory */
+			msr.hi |= 0x20;		/* write serialize PCI memory */
 	}
 
 	/* load up C000 settings in eax. */
 	for ( ; bit; bit--) {
 		msr.lo <<= 8;
-		msr.lo |= 1;				/* cache disable PCI/Shadow memory */
+		msr.lo |= 1;			/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
-			msr.lo |= 0x20;			/* write serialize PCI memory */
+			msr.lo |= 0x20;		/* write serialize PCI memory */
 	}
 
 	wrmsr(CPU_RCONF_C0_DF, msr);
@@ -556,24 +553,23 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
 	/* load up F000 settings in edx. */
 	for (bit = 8; (bit > 4); bit--) {
 		msr.hi <<= 8;
-		msr.hi |= 1;				/* cache disable PCI/Shadow memory */
+		msr.hi |= 1;			/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
-			msr.hi |= 0x20;			/* write serialize PCI memory */
+			msr.hi |= 0x20;		/* write serialize PCI memory */
 	}
 
 	/* load up E000 settings in eax. */
 	for ( ; bit; bit--) {
 		msr.lo <<= 8;
-		msr.lo |= 1;				/* cache disable PCI/Shadow memory */
+		msr.lo |= 1;			/* cache disable PCI/Shadow memory */
 		if (shadowByte && (1 << bit))
-			msr.lo |= 0x20;			/* write serialize PCI memory */
+			msr.lo |= 0x20;		/* write serialize PCI memory */
 	}
 
 	wrmsr(CPU_RCONF_E0_FF, msr);
 }
 
-/*
- * Set the GLPCI registers for the memory hole.
+/* Set the GLPCI registers for the memory hole.
  * Keeps all cache shadow descriptors sync'ed.
  * Entry: EDX:EAX is the shadow settings
  */
@@ -588,8 +584,7 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
 	wrmsr(GLPCI_REN, msr);
 }
 
-/*
- * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
+/* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
  * Keeps all shadow descriptors sync'ed.
  * Entry: EDX:EAX is the shadow settings
  */
@@ -630,8 +625,7 @@ static void shadowRom(void)
 	setShadow(shadowSettings);
 }
 
-/*
- * Set up RCONF_DEFAULT and any other RCONF registers needed.
+/* Set up RCONF_DEFAULT and any other RCONF registers needed.
  *
  * DEVRC_RCONF_DEFAULT:
  * ROMRC(63:56) = 04h	 ; write protect ROMBASE
@@ -645,8 +639,7 @@ static void shadowRom(void)
 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000
 #define ROMRC_RCONF_DEFAULT 0x25
 
-static void
-RCONFInit(void)
+static void RCONFInit(void)
 {
 	struct gliutable *gl = 0;
 	int i;