diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-10-10 12:41:49 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-01-28 23:12:27 +0100 |
| commit | 029aaf627c381a70b365e8b29797425785eb6788 (patch) | |
| tree | 516c4147e7d0c18362b51afd0b200171bd4545ea /src/northbridge | |
| parent | f545abfd22a594ecb9c0678efa5278bb38a37a70 (diff) | |
x86: add common definitions for control registers
The access to control registers were scattered about.
Provide a single header file to provide the correct
access function and definitions.
BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted using this infrastructure. Also objdump'd the
assembly to ensure consistency (objdump -d -r -S | grep xmm).
Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172641
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4873
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/raminit_f_dqs.c | 14 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 14 | ||||
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 12 |
3 files changed, 3 insertions, 37 deletions
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 0781c7939b..8ab1b47fe8 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -19,6 +19,7 @@ */ #include <arch/stages.h> +#include <cpu/x86/cr.h> //0: mean no debug info #define DQS_TRAIN_DEBUG 0 @@ -114,19 +115,6 @@ static unsigned Get_RcvrSysAddr(const struct mem_controller * ctrl, unsigned cha } -static inline unsigned long read_cr4(void) -{ - unsigned long cr4; - asm volatile ("movl %%cr4, %0" : "=r" (cr4)); - return cr4; -} - -static inline void write_cr4(unsigned long cr4) -{ - asm volatile ("movl %0, %%cr4" : : "r" (cr4)); -} - - static inline void enable_sse2(void) { unsigned long cr4; diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h index 2090e0840b..e989ae37c4 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h @@ -99,19 +99,7 @@ static u32 bsf(u32 x) /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") -static inline u32 read_cr4(void) -{ - u32 cr4; - __asm__ volatile ("movl %%cr4, %0" : "=r" (cr4)); - return cr4; -} - - -static inline void write_cr4(u32 cr4) -{ - __asm__ volatile ("movl %0, %%cr4" : : "r" (cr4)); -} - +#include <cpu/x86/cr.h> u32 SetUpperFSbase(u32 addr_hi); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h index 4e5bca278a..abe6e7bd3f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h @@ -93,17 +93,7 @@ static u32 bsf(u32 x) /* prevent speculative execution of following instructions */ #define _EXECFENCE asm volatile ("outb %al, $0xed") -static inline u32 read_cr4(void) -{ - u32 cr4; - __asm__ volatile ("movl %%cr4, %0" : "=r" (cr4)); - return cr4; -} - -static inline void write_cr4(u32 cr4) -{ - __asm__ volatile ("movl %0, %%cr4" : : "r" (cr4)); -} +#include <cpu/x86/cr.h> u32 SetUpperFSbase(u32 addr_hi); |